-
Notifications
You must be signed in to change notification settings - Fork 96
Nexus 9 (Tegra TK1 T132 Denver)
Cosmin Gorgovan edited this page Mar 31, 2016
·
1 revision
Note that the frequency is capped to 1.63 GHz to avoid thermal throttling. This tablet can't run at the maximum frequency under full load on one core for more than half a minute or so.
Processor : NVIDIA Denver 1.0 rev 0 (aarch64) processor : 0 processor : 1 Features : fp asimd aes pmull sha1 sha2 crc32 wp half thumb fastmult vfp edsp neon vfpv3 tlsi vfpv4 idiva idivt CPU implementer : 0x4e CPU architecture: 8 CPU variant : 0x0 CPU part : 0x000 CPU revision : 0 Hardware : Flounder Revision : 0000 Serial : 0000000000000000 MTS version : 33985182
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 4572.7 MB/s (0.8%)
C copy backwards (32 byte blocks) : 4535.5 MB/s (2.8%)
C copy backwards (64 byte blocks) : 4583.8 MB/s (0.7%)
C copy : 4451.8 MB/s (0.5%)
C copy prefetched (32 bytes step) : 4502.2 MB/s (0.6%)
C copy prefetched (64 bytes step) : 4498.2 MB/s (0.5%)
C 2-pass copy : 2781.3 MB/s (0.7%)
C 2-pass copy prefetched (32 bytes step) : 2784.5 MB/s (3.0%)
C 2-pass copy prefetched (64 bytes step) : 2790.4 MB/s (1.0%)
C fill : 9115.3 MB/s (0.4%)
C fill (shuffle within 16 byte blocks) : 9111.7 MB/s (0.3%)
C fill (shuffle within 32 byte blocks) : 9114.4 MB/s (0.5%)
C fill (shuffle within 64 byte blocks) : 9184.8 MB/s (0.5%)
---
standard memcpy : 3629.8 MB/s (0.9%)
standard memset : 4895.6 MB/s (1.8%)
---
NEON read : 9354.2 MB/s (1.3%)
NEON read prefetched (32 bytes step) : 9358.8 MB/s (0.4%)
NEON read prefetched (64 bytes step) : 9355.2 MB/s (0.5%)
NEON read 2 data streams : 9239.0 MB/s (0.5%)
NEON read 2 data streams prefetched (32 bytes step) : 9239.5 MB/s (0.7%)
NEON read 2 data streams prefetched (64 bytes step) : 9123.2 MB/s (0.8%)
NEON copy : 3723.7 MB/s (4.5%)
NEON copy prefetched (32 bytes step) : 3748.4 MB/s (1.1%)
NEON copy prefetched (64 bytes step) : 4938.0 MB/s (0.7%)
NEON unrolled copy : 4678.1 MB/s (0.5%)
NEON unrolled copy prefetched (32 bytes step) : 4690.9 MB/s (1.1%)
NEON unrolled copy prefetched (64 bytes step) : 4625.2 MB/s (0.3%)
NEON copy backwards : 3529.3 MB/s (0.4%)
NEON copy backwards prefetched (32 bytes step) : 3932.7 MB/s (4.8%)
NEON copy backwards prefetched (64 bytes step) : 3778.2 MB/s (1.1%)
NEON 2-pass copy : 2605.3 MB/s (0.9%)
NEON 2-pass copy prefetched (32 bytes step) : 2603.1 MB/s (0.2%)
NEON 2-pass copy prefetched (64 bytes step) : 4081.7 MB/s (0.4%)
NEON unrolled 2-pass copy : 3460.3 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 3502.4 MB/s (0.7%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 3502.0 MB/s (0.5%)
NEON fill : 9904.5 MB/s (0.3%)
NEON fill backwards : 7053.0 MB/s (0.3%)
VFP copy : 4946.0 MB/s (3.3%)
VFP 2-pass copy : 4013.9 MB/s (0.8%)
ARM fill (STRD) : 8438.4 MB/s (0.2%)
ARM fill (STM with 8 registers) : 8440.1 MB/s (0.2%)
ARM fill (STM with 4 registers) : 8438.9 MB/s (0.2%)
ARM copy prefetched (incr pld) : 4596.5 MB/s (0.1%)
ARM copy prefetched (wrap pld) : 4594.0 MB/s (0.2%)
ARM 2-pass copy prefetched (incr pld) : 3292.6 MB/s (0.2%)
ARM 2-pass copy prefetched (wrap pld) : 3289.5 MB/s (0.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.1 ns / 0.1 ns
4096 : 0.1 ns / 0.1 ns
8192 : 0.1 ns / 0.1 ns
16384 : 0.0 ns / 0.1 ns
32768 : 0.0 ns / 0.1 ns
65536 : 0.1 ns / 0.1 ns
131072 : 5.8 ns / 9.6 ns
262144 : 8.7 ns / 13.2 ns
524288 : 10.3 ns / 14.8 ns
1048576 : 11.7 ns / 16.2 ns
2097152 : 35.9 ns / 57.4 ns
4194304 : 88.1 ns / 124.3 ns
8388608 : 117.2 ns / 147.7 ns
16777216 : 144.4 ns / 169.9 ns
33554432 : 157.1 ns / 177.9 ns
67108864 : 165.0 ns / 184.5 ns
Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.
tinymembench v0.4.9 (simple benchmark for memory thr
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2949.7 MB/s (3.8%)
C copy backwards (32 byte blocks) : 3011.8 MB/s
C copy backwards (64 byte blocks) : 3029.2 MB/s
C copy : 3642.2 MB/s (4.1%)
C copy prefetched (32 bytes step) : 3824.4 MB/s (0.3%)
C copy prefetched (64 bytes step) : 3825.3 MB/s (0.4%)
C 2-pass copy : 2726.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 2902.6 MB/s (2.5%)
C 2-pass copy prefetched (64 bytes step) : 2928.3 MB/s (0.3%)
C fill : 8541.0 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 8518.5 MB/s (2.1%)
C fill (shuffle within 32 byte blocks) : 8537.1 MB/s (0.1%)
C fill (shuffle within 64 byte blocks) : 8528.7 MB/s (0.2%)
---
standard memcpy : 3558.8 MB/s
standard memset : 8520.2 MB/s
---
NEON LDP/STP copy : 3633.9 MB/s (4.2%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1451.0 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1450.9 MB/s (0.5%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 3882.5 MB/s (3.9%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 3884.0 MB/s (0.4%)
NEON LD1/ST1 copy : 3630.8 MB/s (0.3%)
NEON STP fill : 8537.8 MB/s
NEON STNP fill : 8544.9 MB/s (1.7%)
ARM LDP/STP copy : 3635.8 MB/s (0.3%)
ARM STP fill : 8544.8 MB/s (0.1%)
ARM STNP fill : 8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 766.0 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 688.8 MB/s
NEON LD1/ST1 copy (from framebuffer) : 770.6 MB/s (0.1%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 681.3 MB/s (0.3%)
ARM LDP/STP copy (from framebuffer) : 766.1 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 689.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.1 ns / 0.1 ns
32768 : 1.7 ns / 2.9 ns
65536 : 6.4 ns / 9.5 ns
131072 : 9.6 ns / 12.3 ns
262144 : 13.7 ns / 17.0 ns
524288 : 15.8 ns / 19.7 ns
1048576 : 17.3 ns / 22.1 ns
2097152 : 42.1 ns / 64.2 ns
4194304 : 98.5 ns / 138.1 ns
8388608 : 143.9 ns / 186.3 ns
16777216 : 167.2 ns / 211.2 ns
33554432 : 180.1 ns / 227.1 ns
67108864 : 200.0 ns / 260.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.4 ns / 9.4 ns
131072 : 9.5 ns / 12.2 ns
262144 : 11.2 ns / 13.1 ns
524288 : 12.1 ns / 13.5 ns
1048576 : 12.8 ns / 13.6 ns
2097152 : 27.0 ns / 33.0 ns
4194304 : 90.6 ns / 127.8 ns
8388608 : 123.9 ns / 153.8 ns
16777216 : 139.5 ns / 161.2 ns
33554432 : 147.2 ns / 163.6 ns
67108864 : 154.0 ns / 167.6 ns