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Allwinner a20
Siarhei Siamashka edited this page Jun 30, 2013
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Using the bootloader from nand firmware cb_a20_ubn_12.04_x-v1.02-dram480.img on CubieBoard2. The kernel is from https://github.com/cubieboard2/linux-sunxi/tree/sunxi-3.3-cb2 (and has framebuffer disabled).
echo 1008000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
Processor : ARMv7 Processor rev 4 (v7l) processor : 0 BogoMIPS : 2000.99 processor : 1 BogoMIPS : 2015.48 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 4 Hardware : sun7i Revision : 0000 Serial : 00000000000000000000000000000000
a10-meminfo-static
dram_clk = 480 dram_type = 3 dram_rank_num = 1 dram_chip_density = 4096 dram_io_width = 16 dram_bus_width = 32 dram_cas = 9 dram_zq = 0x7f dram_odt_en = 0 dram_tpr0 = 0x42d899b7 dram_tpr1 = 0xa090 dram_tpr2 = 0x22a00 dram_tpr3 = 0x0 dram_emr1 = 0x4 dram_emr2 = 0x10 dram_emr3 = 0x0
tinymembench v0.2.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 855.5 MB/s (0.3%)
C copy : 902.6 MB/s
C copy prefetched (32 bytes step) : 871.2 MB/s
C copy prefetched (64 bytes step) : 871.1 MB/s (0.1%)
C 2-pass copy : 735.7 MB/s (0.6%)
C 2-pass copy prefetched (32 bytes step) : 762.6 MB/s (0.6%)
C 2-pass copy prefetched (64 bytes step) : 762.6 MB/s (0.4%)
C fill : 2031.1 MB/s (0.4%)
---
standard memcpy : 931.6 MB/s (0.5%)
standard memset : 2031.3 MB/s (0.5%)
---
NEON read : 1231.8 MB/s (0.3%)
NEON read prefetched (32 bytes step) : 1325.4 MB/s (0.5%)
NEON read prefetched (64 bytes step) : 1405.4 MB/s (0.4%)
NEON copy : 904.7 MB/s
NEON copy prefetched (32 bytes step) : 916.5 MB/s
NEON copy prefetched (64 bytes step) : 949.1 MB/s
NEON unrolled copy : 924.3 MB/s
NEON unrolled copy prefetched (32 bytes step) : 845.6 MB/s (0.1%)
NEON unrolled copy prefetched (64 bytes step) : 878.5 MB/s
NEON copy backwards : 857.1 MB/s
NEON copy backwards prefetched (32 bytes step) : 935.6 MB/s (0.4%)
NEON copy backwards prefetched (64 bytes step) : 927.1 MB/s
NEON 2-pass copy : 760.8 MB/s (0.4%)
NEON 2-pass copy prefetched (32 bytes step) : 798.3 MB/s (0.3%)
NEON 2-pass copy prefetched (64 bytes step) : 808.2 MB/s (0.4%)
NEON unrolled 2-pass copy : 677.7 MB/s (0.3%)
NEON unrolled 2-pass copy prefetched (32 bytes step) : 634.7 MB/s (0.2%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 687.0 MB/s (0.3%)
NEON fill : 2031.8 MB/s (0.4%)
NEON fill backwards : 2032.0 MB/s (0.4%)
ARM fill (STRD) : 2012.5 MB/s
ARM fill (STM with 8 registers) : 2031.4 MB/s (0.3%)
ARM fill (STM with 4 registers) : 2031.0 MB/s (0.4%)
ARM copy prefetched (incr pld) : 920.4 MB/s
ARM copy prefetched (wrap pld) : 865.7 MB/s (0.1%)
ARM 2-pass copy prefetched (incr pld) : 765.6 MB/s (0.3%)
ARM 2-pass copy prefetched (wrap pld) : 735.1 MB/s (0.3%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with total 3 requests to SDRAM for almost every ==
== memory access (though 64MiB is not large enough to experience this ==
== effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : read access time (single random read / dual random read)
2 : 0.0 ns / 0.0 ns
4 : 0.0 ns / 0.0 ns
8 : 0.0 ns / 0.0 ns
16 : 0.0 ns / 0.0 ns
32 : 0.0 ns / 0.0 ns
64 : 0.0 ns / 0.0 ns
128 : 0.0 ns / 0.0 ns
256 : 0.0 ns / 0.0 ns
512 : 0.0 ns / 0.0 ns
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.8 ns / 10.8 ns
131072 : 10.1 ns / 15.1 ns
262144 : 13.0 ns / 18.5 ns
524288 : 105.5 ns / 165.4 ns
1048576 : 157.1 ns / 216.9 ns
2097152 : 190.1 ns / 241.4 ns
4194304 : 207.8 ns / 251.7 ns
8388608 : 218.4 ns / 259.8 ns
16777216 : 229.5 ns / 273.3 ns
33554432 : 245.6 ns / 301.6 ns
67108864 : 277.7 ns / 364.3 ns
Latency test with huge pages enabled:
echo 100 > /proc/sys/vm/nr_hugepages
mount -t hugetlbfs none /mnt/huge
export LD_PRELOAD=libhugetlbfs.so
export HUGETLB_MORECORE=yes
./tinymembench
block size : read access time (single random read / dual random read)
2 : 0.0 ns / 0.0 ns
4 : 0.0 ns / 0.0 ns
8 : 0.0 ns / 0.0 ns
16 : 0.0 ns / 0.0 ns
32 : 0.0 ns / 0.0 ns
64 : 0.0 ns / 0.0 ns
128 : 0.0 ns / 0.0 ns
256 : 0.0 ns / 0.0 ns
512 : 0.0 ns / 0.0 ns
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.3 ns / 10.8 ns
131072 : 10.2 ns / 15.1 ns
262144 : 13.1 ns / 18.5 ns
524288 : 105.5 ns / 165.4 ns
1048576 : 157.0 ns / 216.9 ns
2097152 : 183.5 ns / 234.7 ns
4194304 : 197.5 ns / 241.9 ns
8388608 : 204.4 ns / 244.7 ns
16777216 : 208.0 ns / 246.0 ns
33554432 : 209.5 ns / 246.6 ns
67108864 : 210.3 ns / 246.8 ns
Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.
tinymembench v0.4.9 (simple benchmark for memory thr
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2949.7 MB/s (3.8%)
C copy backwards (32 byte blocks) : 3011.8 MB/s
C copy backwards (64 byte blocks) : 3029.2 MB/s
C copy : 3642.2 MB/s (4.1%)
C copy prefetched (32 bytes step) : 3824.4 MB/s (0.3%)
C copy prefetched (64 bytes step) : 3825.3 MB/s (0.4%)
C 2-pass copy : 2726.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 2902.6 MB/s (2.5%)
C 2-pass copy prefetched (64 bytes step) : 2928.3 MB/s (0.3%)
C fill : 8541.0 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 8518.5 MB/s (2.1%)
C fill (shuffle within 32 byte blocks) : 8537.1 MB/s (0.1%)
C fill (shuffle within 64 byte blocks) : 8528.7 MB/s (0.2%)
---
standard memcpy : 3558.8 MB/s
standard memset : 8520.2 MB/s
---
NEON LDP/STP copy : 3633.9 MB/s (4.2%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1451.0 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1450.9 MB/s (0.5%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 3882.5 MB/s (3.9%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 3884.0 MB/s (0.4%)
NEON LD1/ST1 copy : 3630.8 MB/s (0.3%)
NEON STP fill : 8537.8 MB/s
NEON STNP fill : 8544.9 MB/s (1.7%)
ARM LDP/STP copy : 3635.8 MB/s (0.3%)
ARM STP fill : 8544.8 MB/s (0.1%)
ARM STNP fill : 8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 766.0 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 688.8 MB/s
NEON LD1/ST1 copy (from framebuffer) : 770.6 MB/s (0.1%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 681.3 MB/s (0.3%)
ARM LDP/STP copy (from framebuffer) : 766.1 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 689.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.1 ns / 0.1 ns
32768 : 1.7 ns / 2.9 ns
65536 : 6.4 ns / 9.5 ns
131072 : 9.6 ns / 12.3 ns
262144 : 13.7 ns / 17.0 ns
524288 : 15.8 ns / 19.7 ns
1048576 : 17.3 ns / 22.1 ns
2097152 : 42.1 ns / 64.2 ns
4194304 : 98.5 ns / 138.1 ns
8388608 : 143.9 ns / 186.3 ns
16777216 : 167.2 ns / 211.2 ns
33554432 : 180.1 ns / 227.1 ns
67108864 : 200.0 ns / 260.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.4 ns / 9.4 ns
131072 : 9.5 ns / 12.2 ns
262144 : 11.2 ns / 13.1 ns
524288 : 12.1 ns / 13.5 ns
1048576 : 12.8 ns / 13.6 ns
2097152 : 27.0 ns / 33.0 ns
4194304 : 90.6 ns / 127.8 ns
8388608 : 123.9 ns / 153.8 ns
16777216 : 139.5 ns / 161.2 ns
33554432 : 147.2 ns / 163.6 ns
67108864 : 154.0 ns / 167.6 ns