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IGEPv2 board (DM3730)
Siarhei Siamashka edited this page Mar 30, 2016
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Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS : 996.74 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part : 0xc08 CPU revision : 2 Hardware : IGEP0020 board Revision : 0000 Serial : 0000000000000000
tinymembench v0.4 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 287.8 MB/s (1.3%)
C copy backwards (32 byte blocks) : 277.6 MB/s (1.2%)
C copy backwards (64 byte blocks) : 277.6 MB/s
C copy : 276.4 MB/s (0.3%)
C copy prefetched (32 bytes step) : 503.0 MB/s
C copy prefetched (64 bytes step) : 499.5 MB/s
C 2-pass copy : 240.6 MB/s
C 2-pass copy prefetched (32 bytes step) : 429.9 MB/s
C 2-pass copy prefetched (64 bytes step) : 434.3 MB/s
C fill : 1551.3 MB/s
C fill (shuffle within 16 byte blocks) : 1551.4 MB/s
C fill (shuffle within 32 byte blocks) : 1548.2 MB/s
C fill (shuffle within 64 byte blocks) : 1378.8 MB/s
---
standard memcpy : 421.5 MB/s
standard memset : 1551.0 MB/s
---
NEON read : 1128.2 MB/s
NEON read prefetched (32 bytes step) : 874.8 MB/s
NEON read prefetched (64 bytes step) : 876.7 MB/s
NEON read 2 data streams : 1204.5 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 912.6 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 933.3 MB/s
NEON copy : 538.9 MB/s
NEON copy prefetched (32 bytes step) : 544.4 MB/s
NEON copy prefetched (64 bytes step) : 545.3 MB/s
NEON unrolled copy : 542.3 MB/s
NEON unrolled copy prefetched (32 bytes step) : 613.1 MB/s
NEON unrolled copy prefetched (64 bytes step) : 608.7 MB/s
NEON copy backwards : 538.8 MB/s
NEON copy backwards prefetched (32 bytes step) : 545.0 MB/s
NEON copy backwards prefetched (64 bytes step) : 545.6 MB/s
NEON 2-pass copy : 568.6 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 542.0 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 543.5 MB/s
NEON unrolled 2-pass copy : 583.7 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 527.0 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 531.5 MB/s
NEON fill : 1552.0 MB/s
NEON fill backwards : 1551.6 MB/s
VFP copy : 405.1 MB/s
VFP 2-pass copy : 393.7 MB/s
ARM fill (STRD) : 1551.1 MB/s
ARM fill (STM with 8 registers) : 1551.5 MB/s
ARM fill (STM with 4 registers) : 1551.2 MB/s
ARM copy prefetched (incr pld) : 515.9 MB/s
ARM copy prefetched (wrap pld) : 500.6 MB/s
ARM 2-pass copy prefetched (incr pld) : 485.2 MB/s
ARM 2-pass copy prefetched (wrap pld) : 484.0 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 9.0 ns
131072 : 8.0 ns / 16.2 ns
262144 : 29.1 ns / 57.5 ns
524288 : 116.7 ns / 232.2 ns
1048576 : 162.3 ns / 320.2 ns
2097152 : 185.7 ns / 365.1 ns
4194304 : 198.4 ns / 389.3 ns
8388608 : 206.5 ns / 404.6 ns
16777216 : 215.0 ns / 420.8 ns
33554432 : 227.2 ns / 445.2 ns
67108864 : 249.2 ns / 490.1 ns
Driving a 1280x1024-32@57Hz HDMI monitor
tinymembench v0.4 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 234.8 MB/s (1.4%)
C copy backwards (32 byte blocks) : 266.6 MB/s (1.5%)
C copy backwards (64 byte blocks) : 260.5 MB/s (1.5%)
C copy : 261.2 MB/s
C copy prefetched (32 bytes step) : 324.1 MB/s
C copy prefetched (64 bytes step) : 338.0 MB/s
C 2-pass copy : 223.5 MB/s
C 2-pass copy prefetched (32 bytes step) : 313.3 MB/s
C 2-pass copy prefetched (64 bytes step) : 313.4 MB/s
C fill : 820.1 MB/s
C fill (shuffle within 16 byte blocks) : 819.6 MB/s
C fill (shuffle within 32 byte blocks) : 819.9 MB/s
C fill (shuffle within 64 byte blocks) : 814.5 MB/s
---
standard memcpy : 307.0 MB/s
standard memset : 819.5 MB/s
---
NEON read : 923.7 MB/s
NEON read prefetched (32 bytes step) : 726.3 MB/s
NEON read prefetched (64 bytes step) : 728.8 MB/s
NEON read 2 data streams : 910.6 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 755.8 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 763.5 MB/s
NEON copy : 346.1 MB/s
NEON copy prefetched (32 bytes step) : 347.2 MB/s
NEON copy prefetched (64 bytes step) : 347.0 MB/s
NEON unrolled copy : 345.5 MB/s
NEON unrolled copy prefetched (32 bytes step) : 394.9 MB/s
NEON unrolled copy prefetched (64 bytes step) : 393.3 MB/s
NEON copy backwards : 348.5 MB/s
NEON copy backwards prefetched (32 bytes step) : 353.8 MB/s
NEON copy backwards prefetched (64 bytes step) : 352.5 MB/s
NEON 2-pass copy : 390.4 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 359.2 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 359.3 MB/s
NEON unrolled 2-pass copy : 391.6 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 351.3 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 353.8 MB/s
NEON fill : 819.9 MB/s
NEON fill backwards : 937.7 MB/s
VFP copy : 308.8 MB/s
VFP 2-pass copy : 307.9 MB/s
ARM fill (STRD) : 820.0 MB/s
ARM fill (STM with 8 registers) : 820.0 MB/s
ARM fill (STM with 4 registers) : 820.1 MB/s
ARM copy prefetched (incr pld) : 332.2 MB/s
ARM copy prefetched (wrap pld) : 331.0 MB/s
ARM 2-pass copy prefetched (incr pld) : 312.6 MB/s
ARM 2-pass copy prefetched (wrap pld) : 312.6 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON read (from framebuffer) : 929.4 MB/s
NEON copy (from framebuffer) : 310.0 MB/s
NEON 2-pass copy (from framebuffer) : 379.7 MB/s
NEON unrolled copy (from framebuffer) : 294.8 MB/s
NEON 2-pass unrolled copy (from framebuffer) : 394.3 MB/s
VFP copy (from framebuffer) : 227.2 MB/s
VFP 2-pass copy (from framebuffer) : 310.0 MB/s
ARM copy (from framebuffer) : 54.4 MB/s
ARM 2-pass copy (from framebuffer) : 51.6 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 9.0 ns
131072 : 8.0 ns / 16.2 ns
262144 : 29.3 ns / 57.9 ns
524288 : 121.7 ns / 243.3 ns
1048576 : 169.2 ns / 336.4 ns
2097152 : 193.7 ns / 384.4 ns
4194304 : 206.8 ns / 410.6 ns
8388608 : 215.1 ns / 427.1 ns
16777216 : 223.4 ns / 442.2 ns
33554432 : 226.7 ns / 444.8 ns
67108864 : 249.8 ns / 491.4 ns
Kernel 4.9.140-tegra #1 SMP PREEMPT Wed Mar 13 00:32:22 PDT 2019 aarch64 GNU/Linux Under xorg, no compositor active, no browser or other cpu hogs.
tinymembench v0.4.9 (simple benchmark for memory thr
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2949.7 MB/s (3.8%)
C copy backwards (32 byte blocks) : 3011.8 MB/s
C copy backwards (64 byte blocks) : 3029.2 MB/s
C copy : 3642.2 MB/s (4.1%)
C copy prefetched (32 bytes step) : 3824.4 MB/s (0.3%)
C copy prefetched (64 bytes step) : 3825.3 MB/s (0.4%)
C 2-pass copy : 2726.2 MB/s
C 2-pass copy prefetched (32 bytes step) : 2902.6 MB/s (2.5%)
C 2-pass copy prefetched (64 bytes step) : 2928.3 MB/s (0.3%)
C fill : 8541.0 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 8518.5 MB/s (2.1%)
C fill (shuffle within 32 byte blocks) : 8537.1 MB/s (0.1%)
C fill (shuffle within 64 byte blocks) : 8528.7 MB/s (0.2%)
---
standard memcpy : 3558.8 MB/s
standard memset : 8520.2 MB/s
---
NEON LDP/STP copy : 3633.9 MB/s (4.2%)
NEON LDP/STP copy pldl2strm (32 bytes step) : 1451.0 MB/s (0.3%)
NEON LDP/STP copy pldl2strm (64 bytes step) : 1450.9 MB/s (0.5%)
NEON LDP/STP copy pldl1keep (32 bytes step) : 3882.5 MB/s (3.9%)
NEON LDP/STP copy pldl1keep (64 bytes step) : 3884.0 MB/s (0.4%)
NEON LD1/ST1 copy : 3630.8 MB/s (0.3%)
NEON STP fill : 8537.8 MB/s
NEON STNP fill : 8544.9 MB/s (1.7%)
ARM LDP/STP copy : 3635.8 MB/s (0.3%)
ARM STP fill : 8544.8 MB/s (0.1%)
ARM STNP fill : 8549.2 MB/s (1.0%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
NEON LDP/STP copy (from framebuffer) : 766.0 MB/s
NEON LDP/STP 2-pass copy (from framebuffer) : 688.8 MB/s
NEON LD1/ST1 copy (from framebuffer) : 770.6 MB/s (0.1%)
NEON LD1/ST1 2-pass copy (from framebuffer) : 681.3 MB/s (0.3%)
ARM LDP/STP copy (from framebuffer) : 766.1 MB/s
ARM LDP/STP 2-pass copy (from framebuffer) : 689.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.1 ns / 0.1 ns
32768 : 1.7 ns / 2.9 ns
65536 : 6.4 ns / 9.5 ns
131072 : 9.6 ns / 12.3 ns
262144 : 13.7 ns / 17.0 ns
524288 : 15.8 ns / 19.7 ns
1048576 : 17.3 ns / 22.1 ns
2097152 : 42.1 ns / 64.2 ns
4194304 : 98.5 ns / 138.1 ns
8388608 : 143.9 ns / 186.3 ns
16777216 : 167.2 ns / 211.2 ns
33554432 : 180.1 ns / 227.1 ns
67108864 : 200.0 ns / 260.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.4 ns / 9.4 ns
131072 : 9.5 ns / 12.2 ns
262144 : 11.2 ns / 13.1 ns
524288 : 12.1 ns / 13.5 ns
1048576 : 12.8 ns / 13.6 ns
2097152 : 27.0 ns / 33.0 ns
4194304 : 90.6 ns / 127.8 ns
8388608 : 123.9 ns / 153.8 ns
16777216 : 139.5 ns / 161.2 ns
33554432 : 147.2 ns / 163.6 ns
67108864 : 154.0 ns / 167.6 ns