Apple MacBook Pro (13‐inch, M1, 2020)

tinymembench v0.4.9 (simple benchmark for memory throughput and latency)

========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets ==

C copy backwards : 18351.1 MB/s (0.3%) C copy backwards (32 byte blocks) : 18320.5 MB/s C copy backwards (64 byte blocks) : 18340.9 MB/s (0.2%) C copy : 18397.3 MB/s (0.2%) C copy prefetched (32 bytes step) : 18753.3 MB/s (0.1%) C copy prefetched (64 bytes step) : 18755.4 MB/s (0.2%) C 2-pass copy : 18121.2 MB/s (0.2%) C 2-pass copy prefetched (32 bytes step) : 18418.8 MB/s (0.2%) C 2-pass copy prefetched (64 bytes step) : 18457.5 MB/s (0.2%) C fill : 29758.7 MB/s C fill (shuffle within 16 byte blocks) : 29772.5 MB/s (0.2%) C fill (shuffle within 32 byte blocks) : 29764.4 MB/s (0.2%) C fill (shuffle within 64 byte blocks) : 29759.4 MB/s (0.2%)

standard memcpy : 29071.8 MB/s (0.2%) standard memset : 48748.7 MB/s (1.5%)

NEON LDP/STP copy : 29062.4 MB/s NEON LDP/STP copy pldl2strm (32 bytes step) : 29019.5 MB/s (0.2%) NEON LDP/STP copy pldl2strm (64 bytes step) : 29042.3 MB/s (0.3%) NEON LDP/STP copy pldl1keep (32 bytes step) : 29074.8 MB/s (0.4%) NEON LDP/STP copy pldl1keep (64 bytes step) : 29088.1 MB/s (0.4%) NEON LD1/ST1 copy : 29080.9 MB/s (0.5%) NEON STP fill : 48882.3 MB/s (1.7%) NEON STNP fill : 47623.3 MB/s (1.5%) ARM LDP/STP copy : 29045.0 MB/s (0.2%) ARM STP fill : 48234.0 MB/s (1.8%) ARM STNP fill : 47013.3 MB/s (1.0%)

========================================================================== == Framebuffer read tests. == == == == Many ARM devices use a part of the system memory as the framebuffer, == == typically mapped as uncached but with write-combining enabled. == == Writes to such framebuffers are quite fast, but reads are much == == slower and very sensitive to the alignment and the selection of == == CPU instructions which are used for accessing memory. == == == == Many x86 systems allocate the framebuffer in the GPU memory, == == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == == PCI-E is asymmetric and handles reads a lot worse than writes. == == == == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == == or preferably >300 MB/s), then using the shadow framebuffer layer == == is not necessary in Xorg DDX drivers, resulting in a nice overall == == performance improvement. For example, the xf86-video-fbturbo DDX == == uses this trick. ==

NEON LDP/STP copy (from framebuffer) : 29190.4 MB/s (0.2%) NEON LDP/STP 2-pass copy (from framebuffer) : 19012.5 MB/s (0.2%) NEON LD1/ST1 copy (from framebuffer) : 29177.8 MB/s (0.3%) NEON LD1/ST1 2-pass copy (from framebuffer) : 18987.3 MB/s (0.2%) ARM LDP/STP copy (from framebuffer) : 29172.1 MB/s (0.3%) ARM LDP/STP 2-pass copy (from framebuffer) : 18988.7 MB/s (0.2%)

========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. ==

block size : single random read / dual random read, [MADV_NOHUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 0.0 ns / 0.0 ns 131072 : 0.0 ns / 0.0 ns 262144 : 2.4 ns / 3.5 ns 524288 : 3.5 ns / 4.5 ns 1048576 : 4.1 ns / 4.8 ns 2097152 : 4.5 ns / 4.9 ns 4194304 : 5.4 ns / 5.9 ns 8388608 : 6.7 ns / 7.1 ns 16777216 : 18.1 ns / 28.0 ns 33554432 : 61.5 ns / 91.6 ns 67108864 : 93.5 ns / 122.3 ns

block size : single random read / dual random read, [MADV_HUGEPAGE] 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 0.0 ns / 0.0 ns 131072 : 0.0 ns / 0.0 ns 262144 : 2.3 ns / 3.4 ns 524288 : 3.5 ns / 4.5 ns 1048576 : 4.0 ns / 4.8 ns 2097152 : 4.4 ns / 4.9 ns 4194304 : 4.7 ns / 5.0 ns 8388608 : 4.7 ns / 5.1 ns 16777216 : 16.9 ns / 23.9 ns 33554432 : 60.1 ns / 89.6 ns 67108864 : 90.2 ns / 118.1 ns