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stm32f412 and stm32f413 have a 48MHz clock for SDMMC or USB #82259

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stm32f412 and stm32f413 have a 48MHz clock for SDMMC or USB #82259

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FRASTM
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@FRASTM FRASTM commented Nov 28, 2024 •
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Add the clock configuration for the 48MHz for the stm32f412 or stm32f413 devices
Both have a clock 48MHz which source is PLL Q or PLL I2S Q
This 48MHz clock is feeding the USB or RNG or SDMCC peripherals

Fixes #78816

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FRASTM commented Nov 28, 2024 •
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from the stm32f412 refman:

@FRASTM FRASTM force-pushed the stm32f412_48MHZ branch 2 times, most recently from 3ad12a8 to e310f52 Compare November 28, 2024 14:19
tagunil
tagunil reviewed Nov 28, 2024
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drivers/clock_control/clock_stm32_ll_common.c Outdated
r = -ENOTSUP;
}
break;
#endif /* STM32_SRC_PLLI2S_R */
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Suggested change
#endif /* STM32_SRC_PLLI2S_R */
#endif /* STM32_SRC_PLLI2S_Q */

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done

@FRASTM FRASTM force-pushed the stm32f412_48MHZ branch 2 times, most recently from e18880e to a3a6547 Compare November 28, 2024 14:31
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FRASTM commented Nov 28, 2024

Adding a testcase for the 48MHz clock configuration

west build -p auto -b stm32f412g_disco tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/ -- -DDTC_OVERLAY_FILE="boards/f4_sdmmc48_pll.overlay"

Tested on a stm32f413h_disco,

Running TESTSUITE stm32_common_devices_clocks
===================================================================
START - test_sdmmc_clk_config
SDMMC gating clock on
SDMMC domain clock configured
SDMMC sourced by PLLI2SQ at 48000000 Hz
SDMMC clock rate: 48000000 Hz
SDMMC gating clk off
 PASS - test_sdmmc_clk_config in 0.013 seconds
===================================================================
START - test_sysclk_freq
 PASS - test_sysclk_freq in 0.001 seconds
===================================================================
TESTSUITE stm32_common_devices_clocks succeeded

------ TESTSUITE SUMMARY START ------

SUITE PASS - 100.00% [stm32_common_devices_clocks]: pass = 2, fail = 0, skip = 0, total = 2 duration = 0.014 seconds
 - PASS - [stm32_common_devices_clocks.test_sdmmc_clk_config] duration = 0.013 seconds                                                                                            
 - PASS - [stm32_common_devices_clocks.test_sysclk_freq] duration = 0.001 seconds                                                                                                 
                                                                                                                                                                                  
------ TESTSUITE SUMMARY END ------                                                                                                                                               
                                                                                                                                                                                  
===================================================================                                                                                                               
PROJECT EXECUTION SUCCESSFUL

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FRASTM commented Nov 28, 2024

from the stm32f412 refman:

stm32f412_clock

@FRASTM FRASTM mentioned this pull request Nov 28, 2024
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gautierg-st
gautierg-st requested changes Nov 28, 2024
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include/zephyr/dt-bindings/clock/stm32f410_clock.h Outdated Show resolved Hide resolved
drivers/clock_control/clock_stm32f2_f4_f7.c
Comment on lines +117 to +163
#if STM32_PLLI2S_Q_ENABLED
/* There is a Q divider on the PLLI2S to configure the PLL48CK */
LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
plli2sm(STM32_PLLI2S_M_DIVISOR),
STM32_PLLI2S_N_MULTIPLIER,
plli2sq(STM32_PLLI2S_Q_DIVISOR));
#endif /* STM32_PLLI2S_Q_ENABLED */
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There is currently no configuration of main PLL Q channel. You should also add the LL_RCC_PLL_ConfigDomain_48M function in the config_pll_sysclock function.

include/zephyr/drivers/clock_control/stm32_clock_control.h Show resolved Hide resolved
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FRASTM commented Nov 29, 2024

with new commit 7ffa15a to get the 48MHz freq

gautierg-st
gautierg-st requested changes Nov 29, 2024
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drivers/clock_control/clock_stm32f2_f4_f7.c Outdated Show resolved Hide resolved
drivers/clock_control/clock_stm32f2_f4_f7.c Outdated Show resolved Hide resolved
@FRASTM FRASTM mentioned this pull request Nov 29, 2024
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@FRASTM FRASTM force-pushed the stm32f412_48MHZ branch 5 times, most recently from 94d53ee to a0cb61f Compare November 29, 2024 16:24
@FRASTM
drivers: clock control: stm32F412 has PLL48MHz
eb58631 
Add the configuration of the PLL I2S_Q of the PLLI2S to
set the PLL48MHz clock which feeds the USB, SDMMC, RNG
through the RCC_DCKCFGR2 register.

Signed-off-by: Francois Ramu <[email protected]>
@FRASTM
dts: bindings: pll i2s for the stm32f412 has a Q divider
3449a60 
There is a Q-divider factor [2..15] for the stm32f412 serie
which supplies the 48MHz clock.

Signed-off-by: Francois Ramu <[email protected]>
@FRASTM
dts: arm: stm32f412 device has a clock 48MHz multiplexer
99b1991 
Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.

Signed-off-by: Francois Ramu <[email protected]>
@FRASTM
drivers: clock control: stm32 function to get 48MHz freq
6cf669c 
Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.

Signed-off-by: Francois Ramu <[email protected]>
@FRASTM
tests: drivers: clock: stm32 common device for sdmmc
9c145f9 
Add a testcase for the stm32F412 or stm32F413
configuring the SDIO clock at 48MHz from the PLLI2S
Tested on the stm32f413h disco kit.

Signed-off-by: Francois Ramu <[email protected]>
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stm32f4 sdmmc sdio error clock is not 48MHz
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