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stm32f412 and stm32f413 have a 48MHz clock for SDMMC or USB #82259

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stm32f412 and stm32f413 have a 48MHz clock for SDMMC or USB #82259

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Commits on Nov 29, 2024

  1. drivers: clock control: stm32F412 has PLL48MHz 

    Add the configuration of the PLL I2S_Q of the PLLI2S to
set the PLL48MHz clock which feeds the USB, SDMMC, RNG
through the RCC_DCKCFGR2 register.

Signed-off-by: Francois Ramu <[email protected]>
    @FRASTM
    FRASTM committed Nov 29, 2024
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  2. dts: bindings: pll i2s for the stm32f412 has a Q divider 

    There is a Q-divider factor [2..15] for the stm32f412 serie
which supplies the 48MHz clock.

Signed-off-by: Francois Ramu <[email protected]>
    @FRASTM
    FRASTM committed Nov 29, 2024
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  3. dts: arm: stm32f412 device has a clock 48MHz multiplexer 

    Add a clk48Mhz node to the stm32f412 serie.
This clock is sourced by PLL_Q (default) or PLLI2S_Q
That 48MHz clock is used by the USB /SDMMC/RNG peripherals.

Signed-off-by: Francois Ramu <[email protected]>
    @FRASTM
    FRASTM committed Nov 29, 2024
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  4. drivers: clock control: stm32 function to get 48MHz freq 

    Add a function to compute the clock48 from the clock tree
of a stm32f412/f413 mcu. The value depends on its clock source
Requires to identify the PLL source HSE or HSI.

Signed-off-by: Francois Ramu <[email protected]>
    @FRASTM
    FRASTM committed Nov 29, 2024
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  5. tests: drivers: clock: stm32 common device for sdmmc 

    Add a testcase for the stm32F412 or stm32F413
configuring the SDIO clock at 48MHz from the PLLI2S
Tested on the stm32f413h disco kit.

Signed-off-by: Francois Ramu <[email protected]>
    @FRASTM
    FRASTM committed Nov 29, 2024
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