dts: arm: stm32f412 device has a clock 48MHz multiplexer

Add a clk48Mhz node to the stm32f412 serie. This clock is sourced by PLL_Q (default) or PLLI2S_Q That 48MHz clock is used by the USB /SDMMC/RNG peripherals. Signed-off-by: Francois Ramu <[email protected]>
zephyrproject-rtos · Nov 28, 2024 · e310f52 · e310f52
1 parent ea870ab
commit e310f52
Showing 1 changed file with 7 additions and 2 deletions.
diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi
@@ -16,6 +16,12 @@
 			compatible = "st,stm32f412-plli2s-clock";
 			status = "disabled";
 		};
+
+		clk48: clk48 {
+			#clock-cells = <0>;
+			compatible = "st,stm32-clock-mux";
+			status = "disabled";
+		};
 	};
 
 	soc {
@@ -201,8 +207,7 @@
 		};
 
 		sdmmc1: sdmmc@40012c00 {
-			clocks = <&rcc STM32_CLOCK(APB2, 11U)>,
-				 <&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
+			clocks = <&rcc STM32_CLOCK(APB2, 11U)>;
 		};
 
 		quadspi: quadspi@a0001000 {