Add OpenOCD test #211

RRozak · 2024-07-16T11:38:41Z

It adds OpenOCD test. Parts of the code were copied from caliptra-rtl, mainly from this PR: chipsalliance/caliptra-rtl#72.

Files from axi4_mux were taken from https://github.com/corundum/corundum/blob/master/fpga/lib/axi/rtl/

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-16T11:39:31Z

testbench/ahb_lite_2to1_mux.sv

+    parameter AHB_LITE_ADDR_WIDTH   = 32,
+    parameter AHB_LITE_DATA_WIDTH   = 32,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter AHB_LITE_ADDR_WIDTH = 32,

parameter AHB_LITE_DATA_WIDTH = 32,

parameter AHB_LITE_ADDR_WIDTH = 32,

parameter AHB_LITE_DATA_WIDTH = 32,

github-actions · 2024-07-16T11:39:31Z

testbench/ahb_lite_2to1_mux.sv

+    input logic     hclk,
+    input logic     hreset_n,
+    input logic     force_bus_idle,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic hclk,

input logic hreset_n,

input logic force_bus_idle,

input logic hclk,

input logic hreset_n,

input logic force_bus_idle,

github-actions · 2024-07-16T11:39:32Z

testbench/ahb_lite_2to1_mux.sv

+    input logic                                 hsel_i_0,
+    input logic     [AHB_LITE_ADDR_WIDTH-1:0]   haddr_i_0,
+    input logic     [AHB_LITE_DATA_WIDTH-1:0]   hwdata_i_0,
+    input logic                                 hwrite_i_0,
+    input logic     [1:0]                       htrans_i_0, 
+    input logic     [2:0]                       hsize_i_0,
+    input logic                                 hready_i_0,
+
+    output logic                                hresp_o_0,
+    output logic                                hready_o_0,
+    output logic    [AHB_LITE_DATA_WIDTH-1:0]   hrdata_o_0,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic hsel_i_0,

input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_0,

input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_0,

input logic hwrite_i_0,

input logic [1:0] htrans_i_0,

input logic [2:0] hsize_i_0,

input logic hready_i_0,

output logic hresp_o_0,

output logic hready_o_0,

output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_0,

input logic hsel_i_0,

input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_0,

input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_0,

input logic hwrite_i_0,

input logic [ 1:0] htrans_i_0,

input logic [ 2:0] hsize_i_0,

input logic hready_i_0,

output logic hresp_o_0,

output logic hready_o_0,

output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_0,

github-actions · 2024-07-16T11:39:32Z

testbench/ahb_lite_2to1_mux.sv

+    input logic                                 hsel_i_1,
+    input logic     [AHB_LITE_ADDR_WIDTH-1:0]   haddr_i_1,
+    input logic     [AHB_LITE_DATA_WIDTH-1:0]   hwdata_i_1,
+    input logic                                 hwrite_i_1,
+    input logic     [1:0]                       htrans_i_1, 
+    input logic     [2:0]                       hsize_i_1,
+    input logic                                 hready_i_1,
+
+    output logic                                hresp_o_1,
+    output logic                                hready_o_1,
+    output logic    [AHB_LITE_DATA_WIDTH-1:0]   hrdata_o_1,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic hsel_i_1,

input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_1,

input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_1,

input logic hwrite_i_1,

input logic [1:0] htrans_i_1,

input logic [2:0] hsize_i_1,

input logic hready_i_1,

output logic hresp_o_1,

output logic hready_o_1,

output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_1,

input logic hsel_i_1,

input logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_i_1,

input logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_i_1,

input logic hwrite_i_1,

input logic [ 1:0] htrans_i_1,

input logic [ 2:0] hsize_i_1,

input logic hready_i_1,

output logic hresp_o_1,

output logic hready_o_1,

output logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_o_1,

github-actions · 2024-07-16T11:39:32Z

testbench/ahb_lite_2to1_mux.sv

+    input logic                                 hresp_i,
+    input logic     [AHB_LITE_DATA_WIDTH-1:0]   hrdata_i, 
+    input logic                                 hreadyout_i,
+
+    output logic    [AHB_LITE_ADDR_WIDTH-1:0]   haddr_o, 
+    output logic    [AHB_LITE_DATA_WIDTH-1:0]   hwdata_o, 
+    output logic                                hsel_o, 
+    output logic                                hwrite_o, 
+    output logic                                hready_o,
+    output logic    [1:0]                       htrans_o,
+    output logic    [2:0]                       hsize_o


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic hresp_i,

input logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_i,

input logic hreadyout_i,

output logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_o,

output logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_o,

output logic hsel_o,

output logic hwrite_o,

output logic hready_o,

output logic [1:0] htrans_o,

output logic [2:0] hsize_o

input logic hresp_i,

input logic [AHB_LITE_DATA_WIDTH-1:0] hrdata_i,

input logic hreadyout_i,

output logic [AHB_LITE_ADDR_WIDTH-1:0] haddr_o,

output logic [AHB_LITE_DATA_WIDTH-1:0] hwdata_o,

output logic hsel_o,

output logic hwrite_o,

output logic hready_o,

output logic [ 1:0] htrans_o,

output logic [ 2:0] hsize_o

github-actions · 2024-07-16T11:39:34Z

testbench/ahb_sif.sv

+       arready <= 0;
+       rvalid <= 1;
+       rid <= arid;
+       rlast <= 1;
+       rresp <= 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

arready <= 0;

rvalid <= 1;

rid <= arid;

rlast <= 1;

rresp <= 0;

arready <= 0;

rvalid <= 1;

rid <= arid;

rlast <= 1;

rresp <= 0;

github-actions · 2024-07-16T11:39:34Z

testbench/ahb_sif.sv

+       rvalid <= 0;
+       arready <= 1;
+       rlast <= 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

rvalid <= 0;

arready <= 1;

rlast <= 0;

rvalid <= 0;

arready <= 1;

rlast <= 0;

github-actions · 2024-07-16T11:39:34Z

testbench/ahb_sif.sv

+       write_address = awaddr;
+       awready <= 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

write_address = awaddr;

awready <= 0;

write_address = awaddr;

awready <= 0;

github-actions · 2024-07-16T11:39:34Z

testbench/ahb_sif.sv

+     if (wvalid) begin
+        bid    <= awid;
+        bvalid <= 1;
+        wready <= 0;
+        bresp <= 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (wvalid) begin

bid <= awid;

bvalid <= 1;

wready <= 0;

bresp <= 0;

if (wvalid) begin

bid <= awid;

bvalid <= 1;

wready <= 0;

bresp <= 0;

github-actions · 2024-07-16T11:39:34Z

testbench/ahb_sif.sv

+     end if (bready && bvalid) begin
+        bvalid <= 0;
+        awready <= 1;
+        wready <= 1;
+     end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end if (bready && bvalid) begin

bvalid <= 0;

awready <= 1;

wready <= 1;

end

end

if (bready && bvalid) begin

bvalid <= 0;

awready <= 1;

wready <= 1;

end

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-16T11:46:57Z

testbench/axi4_mux/arbiter.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-16T11:46:58Z

testbench/axi4_mux/arbiter.v

+module arbiter #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module arbiter #

(

module arbiter #(

github-actions · 2024-07-16T11:46:58Z

testbench/axi4_mux/arbiter.v

+)
+(
+    input  wire                     clk,
+    input  wire                     rst,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

)

(

input wire clk,

input wire rst,

) (

input wire clk,

input wire rst,

github-actions · 2024-07-16T11:46:58Z

testbench/axi4_mux/arbiter.v

+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input wire [PORTS-1:0] request,

input wire [PORTS-1:0] acknowledge,

input wire [PORTS-1:0] request,

input wire [PORTS-1:0] acknowledge,

github-actions · 2024-07-16T11:46:58Z

testbench/axi4_mux/arbiter.v

+    input  wire [PORTS-1:0]         request,
+    input  wire [PORTS-1:0]         acknowledge,
+
+    output wire [PORTS-1:0]         grant,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output wire [PORTS-1:0] grant,

output wire [ PORTS-1:0] grant,

github-actions · 2024-07-16T11:47:00Z

testbench/axi4_mux/axi_crossbar.v

+    .s_axi_awid(s_axi_awid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awlen(s_axi_awlen),
+    .s_axi_awsize(s_axi_awsize),
+    .s_axi_awburst(s_axi_awburst),
+    .s_axi_awlock(s_axi_awlock),
+    .s_axi_awcache(s_axi_awcache),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_awqos(s_axi_awqos),
+    .s_axi_awuser(s_axi_awuser),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wlast(s_axi_wlast),
+    .s_axi_wuser(s_axi_wuser),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bid(s_axi_bid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_buser(s_axi_buser),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.s_axi_awid(s_axi_awid),

.s_axi_awaddr(s_axi_awaddr),

.s_axi_awlen(s_axi_awlen),

.s_axi_awsize(s_axi_awsize),

.s_axi_awburst(s_axi_awburst),

.s_axi_awlock(s_axi_awlock),

.s_axi_awcache(s_axi_awcache),

.s_axi_awprot(s_axi_awprot),

.s_axi_awqos(s_axi_awqos),

.s_axi_awuser(s_axi_awuser),

.s_axi_awvalid(s_axi_awvalid),

.s_axi_awready(s_axi_awready),

.s_axi_wdata(s_axi_wdata),

.s_axi_wstrb(s_axi_wstrb),

.s_axi_wlast(s_axi_wlast),

.s_axi_wuser(s_axi_wuser),

.s_axi_wvalid(s_axi_wvalid),

.s_axi_wready(s_axi_wready),

.s_axi_bid(s_axi_bid),

.s_axi_bresp(s_axi_bresp),

.s_axi_buser(s_axi_buser),

.s_axi_bvalid(s_axi_bvalid),

.s_axi_bready(s_axi_bready),

.s_axi_awid(s_axi_awid),

.s_axi_awaddr(s_axi_awaddr),

.s_axi_awlen(s_axi_awlen),

.s_axi_awsize(s_axi_awsize),

.s_axi_awburst(s_axi_awburst),

.s_axi_awlock(s_axi_awlock),

.s_axi_awcache(s_axi_awcache),

.s_axi_awprot(s_axi_awprot),

.s_axi_awqos(s_axi_awqos),

.s_axi_awuser(s_axi_awuser),

.s_axi_awvalid(s_axi_awvalid),

.s_axi_awready(s_axi_awready),

.s_axi_wdata(s_axi_wdata),

.s_axi_wstrb(s_axi_wstrb),

.s_axi_wlast(s_axi_wlast),

.s_axi_wuser(s_axi_wuser),

.s_axi_wvalid(s_axi_wvalid),

.s_axi_wready(s_axi_wready),

.s_axi_bid(s_axi_bid),

.s_axi_bresp(s_axi_bresp),

.s_axi_buser(s_axi_buser),

.s_axi_bvalid(s_axi_bvalid),

.s_axi_bready(s_axi_bready),

github-actions · 2024-07-16T11:47:00Z

testbench/axi4_mux/axi_crossbar.v

+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bready(s_axi_bready),
+
+    /*


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/*

/*

github-actions · 2024-07-16T11:47:01Z

testbench/axi4_mux/axi_crossbar.v

+    .m_axi_awid(m_axi_awid),
+    .m_axi_awaddr(m_axi_awaddr),
+    .m_axi_awlen(m_axi_awlen),
+    .m_axi_awsize(m_axi_awsize),
+    .m_axi_awburst(m_axi_awburst),
+    .m_axi_awlock(m_axi_awlock),
+    .m_axi_awcache(m_axi_awcache),
+    .m_axi_awprot(m_axi_awprot),
+    .m_axi_awqos(m_axi_awqos),
+    .m_axi_awregion(m_axi_awregion),
+    .m_axi_awuser(m_axi_awuser),
+    .m_axi_awvalid(m_axi_awvalid),
+    .m_axi_awready(m_axi_awready),
+    .m_axi_wdata(m_axi_wdata),
+    .m_axi_wstrb(m_axi_wstrb),
+    .m_axi_wlast(m_axi_wlast),
+    .m_axi_wuser(m_axi_wuser),
+    .m_axi_wvalid(m_axi_wvalid),
+    .m_axi_wready(m_axi_wready),
+    .m_axi_bid(m_axi_bid),
+    .m_axi_bresp(m_axi_bresp),
+    .m_axi_buser(m_axi_buser),
+    .m_axi_bvalid(m_axi_bvalid),
+    .m_axi_bready(m_axi_bready)
+);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.m_axi_awid(m_axi_awid),

.m_axi_awaddr(m_axi_awaddr),

.m_axi_awlen(m_axi_awlen),

.m_axi_awsize(m_axi_awsize),

.m_axi_awburst(m_axi_awburst),

.m_axi_awlock(m_axi_awlock),

.m_axi_awcache(m_axi_awcache),

.m_axi_awprot(m_axi_awprot),

.m_axi_awqos(m_axi_awqos),

.m_axi_awregion(m_axi_awregion),

.m_axi_awuser(m_axi_awuser),

.m_axi_awvalid(m_axi_awvalid),

.m_axi_awready(m_axi_awready),

.m_axi_wdata(m_axi_wdata),

.m_axi_wstrb(m_axi_wstrb),

.m_axi_wlast(m_axi_wlast),

.m_axi_wuser(m_axi_wuser),

.m_axi_wvalid(m_axi_wvalid),

.m_axi_wready(m_axi_wready),

.m_axi_bid(m_axi_bid),

.m_axi_bresp(m_axi_bresp),

.m_axi_buser(m_axi_buser),

.m_axi_bvalid(m_axi_bvalid),

.m_axi_bready(m_axi_bready)

);

.m_axi_awid(m_axi_awid),

.m_axi_awaddr(m_axi_awaddr),

.m_axi_awlen(m_axi_awlen),

.m_axi_awsize(m_axi_awsize),

.m_axi_awburst(m_axi_awburst),

.m_axi_awlock(m_axi_awlock),

.m_axi_awcache(m_axi_awcache),

.m_axi_awprot(m_axi_awprot),

.m_axi_awqos(m_axi_awqos),

.m_axi_awregion(m_axi_awregion),

.m_axi_awuser(m_axi_awuser),

.m_axi_awvalid(m_axi_awvalid),

.m_axi_awready(m_axi_awready),

.m_axi_wdata(m_axi_wdata),

.m_axi_wstrb(m_axi_wstrb),

.m_axi_wlast(m_axi_wlast),

.m_axi_wuser(m_axi_wuser),

.m_axi_wvalid(m_axi_wvalid),

.m_axi_wready(m_axi_wready),

.m_axi_bid(m_axi_bid),

.m_axi_bresp(m_axi_bresp),

.m_axi_buser(m_axi_buser),

.m_axi_bvalid(m_axi_bvalid),

.m_axi_bready(m_axi_bready)

);

github-actions · 2024-07-16T11:47:01Z

testbench/axi4_mux/axi_crossbar.v

+axi_crossbar_rd #(
+    .S_COUNT(S_COUNT),
+    .M_COUNT(M_COUNT),
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDR_WIDTH(ADDR_WIDTH),
+    .STRB_WIDTH(STRB_WIDTH),
+    .S_ID_WIDTH(S_ID_WIDTH),
+    .M_ID_WIDTH(M_ID_WIDTH),
+    .ARUSER_ENABLE(ARUSER_ENABLE),
+    .ARUSER_WIDTH(ARUSER_WIDTH),
+    .RUSER_ENABLE(RUSER_ENABLE),
+    .RUSER_WIDTH(RUSER_WIDTH),
+    .S_THREADS(S_THREADS),
+    .S_ACCEPT(S_ACCEPT),
+    .M_REGIONS(M_REGIONS),
+    .M_BASE_ADDR(M_BASE_ADDR),
+    .M_ADDR_WIDTH(M_ADDR_WIDTH),
+    .M_CONNECT(M_CONNECT_READ),
+    .M_ISSUE(M_ISSUE),
+    .M_SECURE(M_SECURE),
+    .S_AR_REG_TYPE(S_AR_REG_TYPE),
+    .S_R_REG_TYPE (S_R_REG_TYPE)
+)
+axi_crossbar_rd_inst (
+    .clk(clk),
+    .rst(rst),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

axi_crossbar_rd #(

.S_COUNT(S_COUNT),

.M_COUNT(M_COUNT),

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.S_ID_WIDTH(S_ID_WIDTH),

.M_ID_WIDTH(M_ID_WIDTH),

.ARUSER_ENABLE(ARUSER_ENABLE),

.ARUSER_WIDTH(ARUSER_WIDTH),

.RUSER_ENABLE(RUSER_ENABLE),

.RUSER_WIDTH(RUSER_WIDTH),

.S_THREADS(S_THREADS),

.S_ACCEPT(S_ACCEPT),

.M_REGIONS(M_REGIONS),

.M_BASE_ADDR(M_BASE_ADDR),

.M_ADDR_WIDTH(M_ADDR_WIDTH),

.M_CONNECT(M_CONNECT_READ),

.M_ISSUE(M_ISSUE),

.M_SECURE(M_SECURE),

.S_AR_REG_TYPE(S_AR_REG_TYPE),

.S_R_REG_TYPE (S_R_REG_TYPE)

)

axi_crossbar_rd_inst (

.clk(clk),

.rst(rst),

axi_crossbar_rd #(

.S_COUNT(S_COUNT),

.M_COUNT(M_COUNT),

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.S_ID_WIDTH(S_ID_WIDTH),

.M_ID_WIDTH(M_ID_WIDTH),

.ARUSER_ENABLE(ARUSER_ENABLE),

.ARUSER_WIDTH(ARUSER_WIDTH),

.RUSER_ENABLE(RUSER_ENABLE),

.RUSER_WIDTH(RUSER_WIDTH),

.S_THREADS(S_THREADS),

.S_ACCEPT(S_ACCEPT),

.M_REGIONS(M_REGIONS),

.M_BASE_ADDR(M_BASE_ADDR),

.M_ADDR_WIDTH(M_ADDR_WIDTH),

.M_CONNECT(M_CONNECT_READ),

.M_ISSUE(M_ISSUE),

.M_SECURE(M_SECURE),

.S_AR_REG_TYPE(S_AR_REG_TYPE),

.S_R_REG_TYPE(S_R_REG_TYPE)

) axi_crossbar_rd_inst (

.clk(clk),

.rst(rst),

github-actions · 2024-07-16T11:47:01Z

testbench/axi4_mux/axi_crossbar.v

+    .clk(clk),
+    .rst(rst),
+
+    /*


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/*

/*

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-16T12:54:55Z

testbench/axi4_mux/axi_crossbar.v

+    .s_axi_arid(s_axi_arid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arlen(s_axi_arlen),
+    .s_axi_arsize(s_axi_arsize),
+    .s_axi_arburst(s_axi_arburst),
+    .s_axi_arlock(s_axi_arlock),
+    .s_axi_arcache(s_axi_arcache),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_arqos(s_axi_arqos),
+    .s_axi_aruser(s_axi_aruser),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_rid(s_axi_rid),
+    .s_axi_rdata(s_axi_rdata),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rlast(s_axi_rlast),
+    .s_axi_ruser(s_axi_ruser),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.s_axi_arid(s_axi_arid),

.s_axi_araddr(s_axi_araddr),

.s_axi_arlen(s_axi_arlen),

.s_axi_arsize(s_axi_arsize),

.s_axi_arburst(s_axi_arburst),

.s_axi_arlock(s_axi_arlock),

.s_axi_arcache(s_axi_arcache),

.s_axi_arprot(s_axi_arprot),

.s_axi_arqos(s_axi_arqos),

.s_axi_aruser(s_axi_aruser),

.s_axi_arvalid(s_axi_arvalid),

.s_axi_arready(s_axi_arready),

.s_axi_rid(s_axi_rid),

.s_axi_rdata(s_axi_rdata),

.s_axi_rresp(s_axi_rresp),

.s_axi_rlast(s_axi_rlast),

.s_axi_ruser(s_axi_ruser),

.s_axi_rvalid(s_axi_rvalid),

.s_axi_rready(s_axi_rready),

.s_axi_arid(s_axi_arid),

.s_axi_araddr(s_axi_araddr),

.s_axi_arlen(s_axi_arlen),

.s_axi_arsize(s_axi_arsize),

.s_axi_arburst(s_axi_arburst),

.s_axi_arlock(s_axi_arlock),

.s_axi_arcache(s_axi_arcache),

.s_axi_arprot(s_axi_arprot),

.s_axi_arqos(s_axi_arqos),

.s_axi_aruser(s_axi_aruser),

.s_axi_arvalid(s_axi_arvalid),

.s_axi_arready(s_axi_arready),

.s_axi_rid(s_axi_rid),

.s_axi_rdata(s_axi_rdata),

.s_axi_rresp(s_axi_rresp),

.s_axi_rlast(s_axi_rlast),

.s_axi_ruser(s_axi_ruser),

.s_axi_rvalid(s_axi_rvalid),

.s_axi_rready(s_axi_rready),

github-actions · 2024-07-16T12:54:56Z

testbench/axi4_mux/axi_crossbar.v

+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+
+    /*


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

/*

/*

github-actions · 2024-07-16T12:54:56Z

testbench/axi4_mux/axi_crossbar.v

+    .m_axi_arid(m_axi_arid),
+    .m_axi_araddr(m_axi_araddr),
+    .m_axi_arlen(m_axi_arlen),
+    .m_axi_arsize(m_axi_arsize),
+    .m_axi_arburst(m_axi_arburst),
+    .m_axi_arlock(m_axi_arlock),
+    .m_axi_arcache(m_axi_arcache),
+    .m_axi_arprot(m_axi_arprot),
+    .m_axi_arqos(m_axi_arqos),
+    .m_axi_arregion(m_axi_arregion),
+    .m_axi_aruser(m_axi_aruser),
+    .m_axi_arvalid(m_axi_arvalid),
+    .m_axi_arready(m_axi_arready),
+    .m_axi_rid(m_axi_rid),
+    .m_axi_rdata(m_axi_rdata),
+    .m_axi_rresp(m_axi_rresp),
+    .m_axi_rlast(m_axi_rlast),
+    .m_axi_ruser(m_axi_ruser),
+    .m_axi_rvalid(m_axi_rvalid),
+    .m_axi_rready(m_axi_rready)
+);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

.m_axi_arid(m_axi_arid),

.m_axi_araddr(m_axi_araddr),

.m_axi_arlen(m_axi_arlen),

.m_axi_arsize(m_axi_arsize),

.m_axi_arburst(m_axi_arburst),

.m_axi_arlock(m_axi_arlock),

.m_axi_arcache(m_axi_arcache),

.m_axi_arprot(m_axi_arprot),

.m_axi_arqos(m_axi_arqos),

.m_axi_arregion(m_axi_arregion),

.m_axi_aruser(m_axi_aruser),

.m_axi_arvalid(m_axi_arvalid),

.m_axi_arready(m_axi_arready),

.m_axi_rid(m_axi_rid),

.m_axi_rdata(m_axi_rdata),

.m_axi_rresp(m_axi_rresp),

.m_axi_rlast(m_axi_rlast),

.m_axi_ruser(m_axi_ruser),

.m_axi_rvalid(m_axi_rvalid),

.m_axi_rready(m_axi_rready)

);

.m_axi_arid(m_axi_arid),

.m_axi_araddr(m_axi_araddr),

.m_axi_arlen(m_axi_arlen),

.m_axi_arsize(m_axi_arsize),

.m_axi_arburst(m_axi_arburst),

.m_axi_arlock(m_axi_arlock),

.m_axi_arcache(m_axi_arcache),

.m_axi_arprot(m_axi_arprot),

.m_axi_arqos(m_axi_arqos),

.m_axi_arregion(m_axi_arregion),

.m_axi_aruser(m_axi_aruser),

.m_axi_arvalid(m_axi_arvalid),

.m_axi_arready(m_axi_arready),

.m_axi_rid(m_axi_rid),

.m_axi_rdata(m_axi_rdata),

.m_axi_rresp(m_axi_rresp),

.m_axi_rlast(m_axi_rlast),

.m_axi_ruser(m_axi_ruser),

.m_axi_rvalid(m_axi_rvalid),

.m_axi_rready(m_axi_rready)

);

github-actions · 2024-07-16T12:54:56Z

testbench/axi4_mux/axi_crossbar_addr.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-16T12:54:56Z

testbench/axi4_mux/axi_crossbar_addr.v

+module axi_crossbar_addr #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module axi_crossbar_addr #

(

module axi_crossbar_addr #(

github-actions · 2024-07-16T12:54:58Z

testbench/axi4_mux/axi_crossbar_addr.v

+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin
+            $display("Region not aligned:");
+            $display("%2d (%2d): %x / %2d -- %x-%x",
+                i/M_REGIONS, i%M_REGIONS,
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],
+                M_ADDR_WIDTH[i*32 +: 32],
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),
+                M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))
+            );
+            $error("Error: address range not aligned (instance %m)");
+            $finish;
+        end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin

if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin

$display("Region not aligned:");

$display("%2d (%2d): %x / %2d -- %x-%x",

i/M_REGIONS, i%M_REGIONS,

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],

M_ADDR_WIDTH[i*32 +: 32],

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))

);

$error("Error: address range not aligned (instance %m)");

$finish;

end

for (i = 0; i < M_COUNT * M_REGIONS; i = i + 1) begin

if ((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & (2**M_ADDR_WIDTH[i*32 +: 32]-1)) != 0) begin

$display("Region not aligned:");

$display(

"%2d (%2d): %x / %2d -- %x-%x", i / M_REGIONS, i % M_REGIONS,

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH], M_ADDR_WIDTH[i*32+:32],

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32+:32]),

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32+:32])));

$error("Error: address range not aligned (instance %m)");

$finish;

end

github-actions · 2024-07-16T12:54:58Z

testbench/axi4_mux/axi_crossbar_addr.v

+    for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
+        for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin
+            if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin
+                if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))))


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin

for (j = i+1; j < M_COUNT*M_REGIONS; j = j + 1) begin

if (M_ADDR_WIDTH[i*32 +: 32] && M_ADDR_WIDTH[j*32 +: 32]) begin

if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))))

for (i = 0; i < M_COUNT * M_REGIONS; i = i + 1) begin

for (j = i + 1; j < M_COUNT * M_REGIONS; j = j + 1) begin

if (M_ADDR_WIDTH[i*32+:32] && M_ADDR_WIDTH[j*32+:32]) begin

if (((M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32])) <= (M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))))

github-actions · 2024-07-16T12:54:58Z

testbench/axi4_mux/axi_crossbar_addr.v

+                    $display("Overlapping regions:");
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        i/M_REGIONS, i%M_REGIONS,
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],
+                        M_ADDR_WIDTH[i*32 +: 32],
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),
+                        M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))
+                    );
+                    $display("%2d (%2d): %x / %2d -- %x-%x",
+                        j/M_REGIONS, j%M_REGIONS,
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH],
+                        M_ADDR_WIDTH[j*32 +: 32],
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]),
+                        M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))
+                    );
+                    $error("Error: address ranges overlap (instance %m)");
+                    $finish;
+                end
+            end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

$display("Overlapping regions:");

$display("%2d (%2d): %x / %2d -- %x-%x",

i/M_REGIONS, i%M_REGIONS,

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH],

M_ADDR_WIDTH[i*32 +: 32],

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32 +: 32]),

M_BASE_ADDR_INT[i*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32 +: 32]))

);

$display("%2d (%2d): %x / %2d -- %x-%x",

j/M_REGIONS, j%M_REGIONS,

M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH],

M_ADDR_WIDTH[j*32 +: 32],

M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32 +: 32]),

M_BASE_ADDR_INT[j*ADDR_WIDTH +: ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32 +: 32]))

);

$error("Error: address ranges overlap (instance %m)");

$finish;

end

end

$display("Overlapping regions:");

$display(

"%2d (%2d): %x / %2d -- %x-%x", i / M_REGIONS, i % M_REGIONS,

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH], M_ADDR_WIDTH[i*32+:32],

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[i*32+:32]),

M_BASE_ADDR_INT[i*ADDR_WIDTH+:ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[i*32+:32])));

$display(

"%2d (%2d): %x / %2d -- %x-%x", j / M_REGIONS, j % M_REGIONS,

M_BASE_ADDR_INT[j*ADDR_WIDTH+:ADDR_WIDTH], M_ADDR_WIDTH[j*32+:32],

M_BASE_ADDR_INT[j*ADDR_WIDTH+:ADDR_WIDTH] & ({ADDR_WIDTH{1'b1}} << M_ADDR_WIDTH[j*32+:32]),

M_BASE_ADDR_INT[j*ADDR_WIDTH+:ADDR_WIDTH] | ({ADDR_WIDTH{1'b1}} >> (ADDR_WIDTH - M_ADDR_WIDTH[j*32+:32])));

$error("Error: address ranges overlap (instance %m)");

$finish;

end

github-actions · 2024-07-16T12:54:58Z

testbench/axi4_mux/axi_crossbar_addr.v

+                end
+            end
+        end
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

end

github-actions · 2024-07-16T12:54:58Z

testbench/axi4_mux/axi_crossbar_addr.v

+            end
+        end
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-16T12:56:45Z

testbench/axi4_mux/axi_crossbar_addr.v

+localparam [2:0]
+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

localparam [2:0]

STATE_IDLE = 3'd0,

STATE_DECODE = 3'd1;

localparam [2:0] STATE_IDLE = 3'd0, STATE_DECODE = 3'd1;

github-actions · 2024-07-16T12:56:45Z

testbench/axi4_mux/axi_crossbar_addr.v

+    STATE_IDLE = 3'd0,
+    STATE_DECODE = 3'd1;
+
+reg [2:0] state_reg = STATE_IDLE, state_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

reg [2:0] state_reg = STATE_IDLE, state_next;

reg [2:0] state_reg = STATE_IDLE, state_next;

github-actions · 2024-07-16T12:56:45Z

testbench/axi4_mux/axi_crossbar_addr.v

+
+reg [2:0] state_reg = STATE_IDLE, state_next;
+
+reg s_axi_aready_reg = 0, s_axi_aready_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

reg s_axi_aready_reg = 0, s_axi_aready_next;

reg s_axi_aready_reg = 0, s_axi_aready_next;

github-actions · 2024-07-16T12:56:45Z

testbench/axi4_mux/axi_crossbar_addr.v

+reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;
+reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;
+reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;
+reg m_decerr_reg = 1'b0, m_decerr_next;
+reg m_wc_valid_reg = 1'b0, m_wc_valid_next;
+reg m_rc_valid_reg = 1'b0, m_rc_valid_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;

reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;

reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;

reg m_decerr_reg = 1'b0, m_decerr_next;

reg m_wc_valid_reg = 1'b0, m_wc_valid_next;

reg m_rc_valid_reg = 1'b0, m_rc_valid_next;

reg [3:0] m_axi_aregion_reg = 4'd0, m_axi_aregion_next;

reg [CL_M_COUNT-1:0] m_select_reg = 0, m_select_next;

reg m_axi_avalid_reg = 1'b0, m_axi_avalid_next;

reg m_decerr_reg = 1'b0, m_decerr_next;

reg m_wc_valid_reg = 1'b0, m_wc_valid_next;

reg m_rc_valid_reg = 1'b0, m_rc_valid_next;

github-actions · 2024-07-16T12:56:45Z

testbench/axi4_mux/axi_crossbar_addr.v

+reg m_wc_valid_reg = 1'b0, m_wc_valid_next;
+reg m_rc_valid_reg = 1'b0, m_rc_valid_next;
+
+assign s_axi_aready = s_axi_aready_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign s_axi_aready = s_axi_aready_reg;

assign s_axi_aready = s_axi_aready_reg;

github-actions · 2024-07-16T12:56:48Z

testbench/axi4_mux/axi_crossbar_addr.v

+        state_reg <= STATE_IDLE;
+        s_axi_aready_reg <= 1'b0;
+        m_axi_avalid_reg <= 1'b0;
+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

state_reg <= STATE_IDLE;

s_axi_aready_reg <= 1'b0;

m_axi_avalid_reg <= 1'b0;

m_wc_valid_reg <= 1'b0;

m_rc_valid_reg <= 1'b0;

state_reg <= STATE_IDLE;

s_axi_aready_reg <= 1'b0;

m_axi_avalid_reg <= 1'b0;

m_wc_valid_reg <= 1'b0;

m_rc_valid_reg <= 1'b0;

github-actions · 2024-07-16T12:56:48Z

testbench/axi4_mux/axi_crossbar_addr.v

+        m_wc_valid_reg <= 1'b0;
+        m_rc_valid_reg <= 1'b0;
+
+        trans_count_reg <= 0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

trans_count_reg <= 0;

trans_count_reg <= 0;

github-actions · 2024-07-16T12:56:48Z

testbench/axi4_mux/axi_crossbar_addr.v

+        state_reg <= state_next;
+        s_axi_aready_reg <= s_axi_aready_next;
+        m_axi_avalid_reg <= m_axi_avalid_next;
+        m_wc_valid_reg <= m_wc_valid_next;
+        m_rc_valid_reg <= m_rc_valid_next;
+
+        if (trans_start && !trans_complete) begin
+            trans_count_reg <= trans_count_reg + 1;
+        end else if (!trans_start && trans_complete) begin
+            trans_count_reg <= trans_count_reg - 1;
+        end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

state_reg <= state_next;

s_axi_aready_reg <= s_axi_aready_next;

m_axi_avalid_reg <= m_axi_avalid_next;

m_wc_valid_reg <= m_wc_valid_next;

m_rc_valid_reg <= m_rc_valid_next;

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

state_reg <= state_next;

s_axi_aready_reg <= s_axi_aready_next;

m_axi_avalid_reg <= m_axi_avalid_next;

m_wc_valid_reg <= m_wc_valid_next;

m_rc_valid_reg <= m_rc_valid_next;

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

github-actions · 2024-07-16T12:56:48Z

testbench/axi4_mux/axi_crossbar_addr.v

+    m_axi_aregion_reg <= m_axi_aregion_next;
+    m_select_reg <= m_select_next;
+    m_decerr_reg <= m_decerr_next;
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

github-actions · 2024-07-16T12:56:48Z

testbench/axi4_mux/axi_crossbar_rd.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T06:27:00Z

testbench/axi4_mux/axi_crossbar_rd.v

+module axi_crossbar_rd #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module axi_crossbar_rd #

(

module axi_crossbar_rd #(

github-actions · 2024-07-17T06:27:00Z

testbench/axi4_mux/axi_crossbar_rd.v

+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter STRB_WIDTH = (DATA_WIDTH/8),

parameter STRB_WIDTH = (DATA_WIDTH / 8),

github-actions · 2024-07-17T06:27:00Z

testbench/axi4_mux/axi_crossbar_rd.v

+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),

parameter M_ID_WIDTH = S_ID_WIDTH + $clog2(S_COUNT),

github-actions · 2024-07-17T06:27:01Z

testbench/axi4_mux/axi_crossbar_rd.v

+)
+(
+    input  wire                             clk,
+    input  wire                             rst,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

)

(

input wire clk,

input wire rst,

) (

input wire clk,

input wire rst,

github-actions · 2024-07-17T06:27:01Z

testbench/axi4_mux/axi_crossbar_rd.v

+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_arlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_arsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_arburst,
+    input  wire [S_COUNT-1:0]               s_axi_arlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_arcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_arprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_arqos,
+    input  wire [S_COUNT*ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire [S_COUNT-1:0]               s_axi_arvalid,
+    output wire [S_COUNT-1:0]               s_axi_arready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_rid,
+    output wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [S_COUNT*2-1:0]             s_axi_rresp,
+    output wire [S_COUNT-1:0]               s_axi_rlast,
+    output wire [S_COUNT*RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire [S_COUNT-1:0]               s_axi_rvalid,
+    input  wire [S_COUNT-1:0]               s_axi_rready,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,

input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,

input wire [S_COUNT*8-1:0] s_axi_arlen,

input wire [S_COUNT*3-1:0] s_axi_arsize,

input wire [S_COUNT*2-1:0] s_axi_arburst,

input wire [S_COUNT-1:0] s_axi_arlock,

input wire [S_COUNT*4-1:0] s_axi_arcache,

input wire [S_COUNT*3-1:0] s_axi_arprot,

input wire [S_COUNT*4-1:0] s_axi_arqos,

input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,

input wire [S_COUNT-1:0] s_axi_arvalid,

output wire [S_COUNT-1:0] s_axi_arready,

output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,

output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,

output wire [S_COUNT*2-1:0] s_axi_rresp,

output wire [S_COUNT-1:0] s_axi_rlast,

output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,

output wire [S_COUNT-1:0] s_axi_rvalid,

input wire [S_COUNT-1:0] s_axi_rready,

input wire [ S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,

input wire [ S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,

input wire [ S_COUNT*8-1:0] s_axi_arlen,

input wire [ S_COUNT*3-1:0] s_axi_arsize,

input wire [ S_COUNT*2-1:0] s_axi_arburst,

input wire [ S_COUNT-1:0] s_axi_arlock,

input wire [ S_COUNT*4-1:0] s_axi_arcache,

input wire [ S_COUNT*3-1:0] s_axi_arprot,

input wire [ S_COUNT*4-1:0] s_axi_arqos,

input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,

input wire [ S_COUNT-1:0] s_axi_arvalid,

output wire [ S_COUNT-1:0] s_axi_arready,

output wire [ S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,

output wire [ S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,

output wire [ S_COUNT*2-1:0] s_axi_rresp,

output wire [ S_COUNT-1:0] s_axi_rlast,

output wire [ S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,

output wire [ S_COUNT-1:0] s_axi_rvalid,

input wire [ S_COUNT-1:0] s_axi_rready,

github-actions · 2024-07-17T06:27:03Z

testbench/axi4_mux/axi_crossbar_rd.v

+        // in-flight transaction count
+        wire trans_start;
+        wire trans_complete;
+        reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
+
+        wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                trans_count_reg <= 0;
+            end else begin
+                if (trans_start && !trans_complete) begin
+                    trans_count_reg <= trans_count_reg + 1;
+                end else if (!trans_start && trans_complete) begin
+                    trans_count_reg <= trans_count_reg - 1;
+                end
+            end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// in-flight transaction count

wire trans_start;

wire trans_complete;

reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;

wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;

always @(posedge clk) begin

if (rst) begin

trans_count_reg <= 0;

end else begin

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

end

// in-flight transaction count

wire trans_start;

wire trans_complete;

reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;

wire trans_limit = trans_count_reg >= M_ISSUE[n*32+:32] && !trans_complete;

always @(posedge clk) begin

if (rst) begin

trans_count_reg <= 0;

end else begin

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

github-actions · 2024-07-17T06:27:03Z

testbench/axi4_mux/axi_crossbar_rd.v

+            .rst(rst),
+            .request(a_request),
+            .acknowledge(a_acknowledge),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_encoded(a_grant_encoded)
+        );
+
+        // address mux
+        wire [M_ID_WIDTH-1:0]   s_axi_arid_mux     = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
+        wire [ADDR_WIDTH-1:0]   s_axi_araddr_mux   = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
+        wire [7:0]              s_axi_arlen_mux    = int_s_axi_arlen[a_grant_encoded*8 +: 8];
+        wire [2:0]              s_axi_arsize_mux   = int_s_axi_arsize[a_grant_encoded*3 +: 3];
+        wire [1:0]              s_axi_arburst_mux  = int_s_axi_arburst[a_grant_encoded*2 +: 2];
+        wire                    s_axi_arlock_mux   = int_s_axi_arlock[a_grant_encoded];
+        wire [3:0]              s_axi_arcache_mux  = int_s_axi_arcache[a_grant_encoded*4 +: 4];
+        wire [2:0]              s_axi_arprot_mux   = int_s_axi_arprot[a_grant_encoded*3 +: 3];
+        wire [3:0]              s_axi_arqos_mux    = int_s_axi_arqos[a_grant_encoded*4 +: 4];
+        wire [3:0]              s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];
+        wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux   = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];
+        wire                    s_axi_arvalid_mux  = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
+        wire                    s_axi_arready_mux;
+
+        assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;
+
+        for (m = 0; m < S_COUNT; m = m + 1) begin
+            assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;
+        end
+
+        assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;
+
+        // read response forwarding
+        wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
+
+        assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;
+        assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];
+
+        assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];
+
+        // M side register
+        axi_register_rd #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(M_ID_WIDTH),
+            .ARUSER_ENABLE(ARUSER_ENABLE),
+            .ARUSER_WIDTH(ARUSER_WIDTH),
+            .RUSER_ENABLE(RUSER_ENABLE),
+            .RUSER_WIDTH(RUSER_WIDTH),
+            .AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
+            .R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_arid(s_axi_arid_mux),
+            .s_axi_araddr(s_axi_araddr_mux),
+            .s_axi_arlen(s_axi_arlen_mux),
+            .s_axi_arsize(s_axi_arsize_mux),
+            .s_axi_arburst(s_axi_arburst_mux),
+            .s_axi_arlock(s_axi_arlock_mux),
+            .s_axi_arcache(s_axi_arcache_mux),
+            .s_axi_arprot(s_axi_arprot_mux),
+            .s_axi_arqos(s_axi_arqos_mux),
+            .s_axi_arregion(s_axi_arregion_mux),
+            .s_axi_aruser(s_axi_aruser_mux),
+            .s_axi_arvalid(s_axi_arvalid_mux),
+            .s_axi_arready(s_axi_arready_mux),
+            .s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),
+            .s_axi_rlast(int_m_axi_rlast[n]),
+            .s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .s_axi_rvalid(int_m_axi_rvalid[n]),
+            .s_axi_rready(int_m_axi_rready[n]),
+            .m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_arlen(m_axi_arlen[n*8 +: 8]),
+            .m_axi_arsize(m_axi_arsize[n*3 +: 3]),
+            .m_axi_arburst(m_axi_arburst[n*2 +: 2]),
+            .m_axi_arlock(m_axi_arlock[n]),
+            .m_axi_arcache(m_axi_arcache[n*4 +: 4]),
+            .m_axi_arprot(m_axi_arprot[n*3 +: 3]),
+            .m_axi_arqos(m_axi_arqos[n*4 +: 4]),
+            .m_axi_arregion(m_axi_arregion[n*4 +: 4]),
+            .m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),
+            .m_axi_arvalid(m_axi_arvalid[n]),
+            .m_axi_arready(m_axi_arready[n]),
+            .m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_rresp(m_axi_rresp[n*2 +: 2]),
+            .m_axi_rlast(m_axi_rlast[n]),
+            .m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
+            .m_axi_rvalid(m_axi_rvalid[n]),
+            .m_axi_rready(m_axi_rready[n])
+        );
+    end // m_ifaces
+
+endgenerate


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// address arbitration

wire [S_COUNT-1:0] a_request;

wire [S_COUNT-1:0] a_acknowledge;

wire [S_COUNT-1:0] a_grant;

wire a_grant_valid;

wire [CL_S_COUNT-1:0] a_grant_encoded;

arbiter #(

.PORTS(S_COUNT),

.ARB_TYPE_ROUND_ROBIN(1),

.ARB_BLOCK(1),

.ARB_BLOCK_ACK(1),

.ARB_LSB_HIGH_PRIORITY(1)

)

a_arb_inst (

.clk(clk),

.rst(rst),

.request(a_request),

.acknowledge(a_acknowledge),

.grant(a_grant),

.grant_valid(a_grant_valid),

.grant_encoded(a_grant_encoded)

);

// address mux

wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);

wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];

wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8 +: 8];

wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3 +: 3];

wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2 +: 2];

wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded];

wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4 +: 4];

wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3 +: 3];

wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4 +: 4];

wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];

wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];

wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;

wire s_axi_arready_mux;

assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;

for (m = 0; m < S_COUNT; m = m + 1) begin

assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;

assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;

end

assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;

// read response forwarding

wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;

assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;

assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];

assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];

// M side register

axi_register_rd #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(M_ID_WIDTH),

.ARUSER_ENABLE(ARUSER_ENABLE),

.ARUSER_WIDTH(ARUSER_WIDTH),

.RUSER_ENABLE(RUSER_ENABLE),

.RUSER_WIDTH(RUSER_WIDTH),

.AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),

.R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])

)

reg_inst (

.clk(clk),

.rst(rst),

.s_axi_arid(s_axi_arid_mux),

.s_axi_araddr(s_axi_araddr_mux),

.s_axi_arlen(s_axi_arlen_mux),

.s_axi_arsize(s_axi_arsize_mux),

.s_axi_arburst(s_axi_arburst_mux),

.s_axi_arlock(s_axi_arlock_mux),

.s_axi_arcache(s_axi_arcache_mux),

.s_axi_arprot(s_axi_arprot_mux),

.s_axi_arqos(s_axi_arqos_mux),

.s_axi_arregion(s_axi_arregion_mux),

.s_axi_aruser(s_axi_aruser_mux),

.s_axi_arvalid(s_axi_arvalid_mux),

.s_axi_arready(s_axi_arready_mux),

.s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),

.s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),

.s_axi_rlast(int_m_axi_rlast[n]),

.s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),

.s_axi_rvalid(int_m_axi_rvalid[n]),

.s_axi_rready(int_m_axi_rready[n]),

.m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),

.m_axi_arlen(m_axi_arlen[n*8 +: 8]),

.m_axi_arsize(m_axi_arsize[n*3 +: 3]),

.m_axi_arburst(m_axi_arburst[n*2 +: 2]),

.m_axi_arlock(m_axi_arlock[n]),

.m_axi_arcache(m_axi_arcache[n*4 +: 4]),

.m_axi_arprot(m_axi_arprot[n*3 +: 3]),

.m_axi_arqos(m_axi_arqos[n*4 +: 4]),

.m_axi_arregion(m_axi_arregion[n*4 +: 4]),

.m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),

.m_axi_arvalid(m_axi_arvalid[n]),

.m_axi_arready(m_axi_arready[n]),

.m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),

.m_axi_rresp(m_axi_rresp[n*2 +: 2]),

.m_axi_rlast(m_axi_rlast[n]),

.m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),

.m_axi_rvalid(m_axi_rvalid[n]),

.m_axi_rready(m_axi_rready[n])

);

end // m_ifaces

endgenerate

end

// address arbitration

wire [S_COUNT-1:0] a_request;

wire [S_COUNT-1:0] a_acknowledge;

wire [S_COUNT-1:0] a_grant;

wire a_grant_valid;

wire [CL_S_COUNT-1:0] a_grant_encoded;

arbiter #(

.PORTS(S_COUNT),

.ARB_TYPE_ROUND_ROBIN(1),

.ARB_BLOCK(1),

.ARB_BLOCK_ACK(1),

.ARB_LSB_HIGH_PRIORITY(1)

) a_arb_inst (

.clk(clk),

.rst(rst),

.request(a_request),

.acknowledge(a_acknowledge),

.grant(a_grant),

.grant_valid(a_grant_valid),

.grant_encoded(a_grant_encoded)

);

// address mux

wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);

wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];

wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8+:8];

wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3+:3];

wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2+:2];

wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded];

wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4+:4];

wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3+:3];

wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4+:4];

wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4+:4];

wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];

wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;

wire s_axi_arready_mux;

assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;

for (m = 0; m < S_COUNT; m = m + 1) begin

assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;

assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;

end

assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;

// read response forwarding

wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH+:M_ID_WIDTH] >> S_ID_WIDTH;

assign int_axi_rvalid[n*S_COUNT+:S_COUNT] = int_m_axi_rvalid[n] << r_select;

assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];

assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];

// M side register

axi_register_rd #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(M_ID_WIDTH),

.ARUSER_ENABLE(ARUSER_ENABLE),

.ARUSER_WIDTH(ARUSER_WIDTH),

.RUSER_ENABLE(RUSER_ENABLE),

.RUSER_WIDTH(RUSER_WIDTH),

.AR_REG_TYPE(M_AR_REG_TYPE[n*2+:2]),

.R_REG_TYPE(M_R_REG_TYPE[n*2+:2])

) reg_inst (

.clk(clk),

.rst(rst),

.s_axi_arid(s_axi_arid_mux),

.s_axi_araddr(s_axi_araddr_mux),

.s_axi_arlen(s_axi_arlen_mux),

.s_axi_arsize(s_axi_arsize_mux),

.s_axi_arburst(s_axi_arburst_mux),

.s_axi_arlock(s_axi_arlock_mux),

.s_axi_arcache(s_axi_arcache_mux),

.s_axi_arprot(s_axi_arprot_mux),

.s_axi_arqos(s_axi_arqos_mux),

.s_axi_arregion(s_axi_arregion_mux),

.s_axi_aruser(s_axi_aruser_mux),

.s_axi_arvalid(s_axi_arvalid_mux),

.s_axi_arready(s_axi_arready_mux),

.s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH+:DATA_WIDTH]),

.s_axi_rresp(int_m_axi_rresp[n*2+:2]),

.s_axi_rlast(int_m_axi_rlast[n]),

.s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH+:RUSER_WIDTH]),

.s_axi_rvalid(int_m_axi_rvalid[n]),

.s_axi_rready(int_m_axi_rready[n]),

.m_axi_arid(m_axi_arid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH+:ADDR_WIDTH]),

.m_axi_arlen(m_axi_arlen[n*8+:8]),

.m_axi_arsize(m_axi_arsize[n*3+:3]),

.m_axi_arburst(m_axi_arburst[n*2+:2]),

.m_axi_arlock(m_axi_arlock[n]),

.m_axi_arcache(m_axi_arcache[n*4+:4]),

.m_axi_arprot(m_axi_arprot[n*3+:3]),

.m_axi_arqos(m_axi_arqos[n*4+:4]),

.m_axi_arregion(m_axi_arregion[n*4+:4]),

.m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH+:ARUSER_WIDTH]),

.m_axi_arvalid(m_axi_arvalid[n]),

.m_axi_arready(m_axi_arready[n]),

.m_axi_rid(m_axi_rid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.m_axi_rdata(m_axi_rdata[n*DATA_WIDTH+:DATA_WIDTH]),

.m_axi_rresp(m_axi_rresp[n*2+:2]),

.m_axi_rlast(m_axi_rlast[n]),

.m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH+:RUSER_WIDTH]),

.m_axi_rvalid(m_axi_rvalid[n]),

.m_axi_rready(m_axi_rready[n])

);

end // m_ifaces

endgenerate

github-actions · 2024-07-17T06:27:03Z

testbench/axi4_mux/axi_crossbar_wr.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-17T06:27:03Z

testbench/axi4_mux/axi_crossbar_wr.v

+module axi_crossbar_wr #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module axi_crossbar_wr #

(

module axi_crossbar_wr #(

github-actions · 2024-07-17T06:27:03Z

testbench/axi4_mux/axi_crossbar_wr.v

+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter STRB_WIDTH = (DATA_WIDTH/8),

parameter STRB_WIDTH = (DATA_WIDTH / 8),

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T10:22:37Z

testbench/axi4_mux/axi_crossbar_wr.v

+    parameter S_ID_WIDTH = 8,
+    // Output ID field width (towards AXI slaves)
+    // Additional bits required for response routing
+    parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),

parameter M_ID_WIDTH = S_ID_WIDTH + $clog2(S_COUNT),

github-actions · 2024-07-17T10:22:37Z

testbench/axi4_mux/axi_crossbar_wr.v

+)
+(
+    input  wire                             clk,
+    input  wire                             rst,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

)

(

input wire clk,

input wire rst,

) (

input wire clk,

input wire rst,

github-actions · 2024-07-17T10:22:37Z

testbench/axi4_mux/axi_crossbar_wr.v

+    input  wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [S_COUNT*ADDR_WIDTH-1:0]    s_axi_awaddr,
+    input  wire [S_COUNT*8-1:0]             s_axi_awlen,
+    input  wire [S_COUNT*3-1:0]             s_axi_awsize,
+    input  wire [S_COUNT*2-1:0]             s_axi_awburst,
+    input  wire [S_COUNT-1:0]               s_axi_awlock,
+    input  wire [S_COUNT*4-1:0]             s_axi_awcache,
+    input  wire [S_COUNT*3-1:0]             s_axi_awprot,
+    input  wire [S_COUNT*4-1:0]             s_axi_awqos,
+    input  wire [S_COUNT*AWUSER_WIDTH-1:0]  s_axi_awuser,
+    input  wire [S_COUNT-1:0]               s_axi_awvalid,
+    output wire [S_COUNT-1:0]               s_axi_awready,
+    input  wire [S_COUNT*DATA_WIDTH-1:0]    s_axi_wdata,
+    input  wire [S_COUNT*STRB_WIDTH-1:0]    s_axi_wstrb,
+    input  wire [S_COUNT-1:0]               s_axi_wlast,
+    input  wire [S_COUNT*WUSER_WIDTH-1:0]   s_axi_wuser,
+    input  wire [S_COUNT-1:0]               s_axi_wvalid,
+    output wire [S_COUNT-1:0]               s_axi_wready,
+    output wire [S_COUNT*S_ID_WIDTH-1:0]    s_axi_bid,
+    output wire [S_COUNT*2-1:0]             s_axi_bresp,
+    output wire [S_COUNT*BUSER_WIDTH-1:0]   s_axi_buser,
+    output wire [S_COUNT-1:0]               s_axi_bvalid,
+    input  wire [S_COUNT-1:0]               s_axi_bready,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_awid,

input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,

input wire [S_COUNT*8-1:0] s_axi_awlen,

input wire [S_COUNT*3-1:0] s_axi_awsize,

input wire [S_COUNT*2-1:0] s_axi_awburst,

input wire [S_COUNT-1:0] s_axi_awlock,

input wire [S_COUNT*4-1:0] s_axi_awcache,

input wire [S_COUNT*3-1:0] s_axi_awprot,

input wire [S_COUNT*4-1:0] s_axi_awqos,

input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,

input wire [S_COUNT-1:0] s_axi_awvalid,

output wire [S_COUNT-1:0] s_axi_awready,

input wire [S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,

input wire [S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,

input wire [S_COUNT-1:0] s_axi_wlast,

input wire [S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,

input wire [S_COUNT-1:0] s_axi_wvalid,

output wire [S_COUNT-1:0] s_axi_wready,

output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_bid,

output wire [S_COUNT*2-1:0] s_axi_bresp,

output wire [S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,

output wire [S_COUNT-1:0] s_axi_bvalid,

input wire [S_COUNT-1:0] s_axi_bready,

input wire [ S_COUNT*S_ID_WIDTH-1:0] s_axi_awid,

input wire [ S_COUNT*ADDR_WIDTH-1:0] s_axi_awaddr,

input wire [ S_COUNT*8-1:0] s_axi_awlen,

input wire [ S_COUNT*3-1:0] s_axi_awsize,

input wire [ S_COUNT*2-1:0] s_axi_awburst,

input wire [ S_COUNT-1:0] s_axi_awlock,

input wire [ S_COUNT*4-1:0] s_axi_awcache,

input wire [ S_COUNT*3-1:0] s_axi_awprot,

input wire [ S_COUNT*4-1:0] s_axi_awqos,

input wire [S_COUNT*AWUSER_WIDTH-1:0] s_axi_awuser,

input wire [ S_COUNT-1:0] s_axi_awvalid,

output wire [ S_COUNT-1:0] s_axi_awready,

input wire [ S_COUNT*DATA_WIDTH-1:0] s_axi_wdata,

input wire [ S_COUNT*STRB_WIDTH-1:0] s_axi_wstrb,

input wire [ S_COUNT-1:0] s_axi_wlast,

input wire [ S_COUNT*WUSER_WIDTH-1:0] s_axi_wuser,

input wire [ S_COUNT-1:0] s_axi_wvalid,

output wire [ S_COUNT-1:0] s_axi_wready,

output wire [ S_COUNT*S_ID_WIDTH-1:0] s_axi_bid,

output wire [ S_COUNT*2-1:0] s_axi_bresp,

output wire [ S_COUNT*BUSER_WIDTH-1:0] s_axi_buser,

output wire [ S_COUNT-1:0] s_axi_bvalid,

input wire [ S_COUNT-1:0] s_axi_bready,

github-actions · 2024-07-17T10:22:37Z

testbench/axi4_mux/axi_crossbar_wr.v

+    output wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_awid,
+    output wire [M_COUNT*ADDR_WIDTH-1:0]    m_axi_awaddr,
+    output wire [M_COUNT*8-1:0]             m_axi_awlen,
+    output wire [M_COUNT*3-1:0]             m_axi_awsize,
+    output wire [M_COUNT*2-1:0]             m_axi_awburst,
+    output wire [M_COUNT-1:0]               m_axi_awlock,
+    output wire [M_COUNT*4-1:0]             m_axi_awcache,
+    output wire [M_COUNT*3-1:0]             m_axi_awprot,
+    output wire [M_COUNT*4-1:0]             m_axi_awqos,
+    output wire [M_COUNT*4-1:0]             m_axi_awregion,
+    output wire [M_COUNT*AWUSER_WIDTH-1:0]  m_axi_awuser,
+    output wire [M_COUNT-1:0]               m_axi_awvalid,
+    input  wire [M_COUNT-1:0]               m_axi_awready,
+    output wire [M_COUNT*DATA_WIDTH-1:0]    m_axi_wdata,
+    output wire [M_COUNT*STRB_WIDTH-1:0]    m_axi_wstrb,
+    output wire [M_COUNT-1:0]               m_axi_wlast,
+    output wire [M_COUNT*WUSER_WIDTH-1:0]   m_axi_wuser,
+    output wire [M_COUNT-1:0]               m_axi_wvalid,
+    input  wire [M_COUNT-1:0]               m_axi_wready,
+    input  wire [M_COUNT*M_ID_WIDTH-1:0]    m_axi_bid,
+    input  wire [M_COUNT*2-1:0]             m_axi_bresp,
+    input  wire [M_COUNT*BUSER_WIDTH-1:0]   m_axi_buser,
+    input  wire [M_COUNT-1:0]               m_axi_bvalid,
+    output wire [M_COUNT-1:0]               m_axi_bready


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_awid,

output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,

output wire [M_COUNT*8-1:0] m_axi_awlen,

output wire [M_COUNT*3-1:0] m_axi_awsize,

output wire [M_COUNT*2-1:0] m_axi_awburst,

output wire [M_COUNT-1:0] m_axi_awlock,

output wire [M_COUNT*4-1:0] m_axi_awcache,

output wire [M_COUNT*3-1:0] m_axi_awprot,

output wire [M_COUNT*4-1:0] m_axi_awqos,

output wire [M_COUNT*4-1:0] m_axi_awregion,

output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,

output wire [M_COUNT-1:0] m_axi_awvalid,

input wire [M_COUNT-1:0] m_axi_awready,

output wire [M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,

output wire [M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,

output wire [M_COUNT-1:0] m_axi_wlast,

output wire [M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,

output wire [M_COUNT-1:0] m_axi_wvalid,

input wire [M_COUNT-1:0] m_axi_wready,

input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_bid,

input wire [M_COUNT*2-1:0] m_axi_bresp,

input wire [M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,

input wire [M_COUNT-1:0] m_axi_bvalid,

output wire [M_COUNT-1:0] m_axi_bready

output wire [ M_COUNT*M_ID_WIDTH-1:0] m_axi_awid,

output wire [ M_COUNT*ADDR_WIDTH-1:0] m_axi_awaddr,

output wire [ M_COUNT*8-1:0] m_axi_awlen,

output wire [ M_COUNT*3-1:0] m_axi_awsize,

output wire [ M_COUNT*2-1:0] m_axi_awburst,

output wire [ M_COUNT-1:0] m_axi_awlock,

output wire [ M_COUNT*4-1:0] m_axi_awcache,

output wire [ M_COUNT*3-1:0] m_axi_awprot,

output wire [ M_COUNT*4-1:0] m_axi_awqos,

output wire [ M_COUNT*4-1:0] m_axi_awregion,

output wire [M_COUNT*AWUSER_WIDTH-1:0] m_axi_awuser,

output wire [ M_COUNT-1:0] m_axi_awvalid,

input wire [ M_COUNT-1:0] m_axi_awready,

output wire [ M_COUNT*DATA_WIDTH-1:0] m_axi_wdata,

output wire [ M_COUNT*STRB_WIDTH-1:0] m_axi_wstrb,

output wire [ M_COUNT-1:0] m_axi_wlast,

output wire [ M_COUNT*WUSER_WIDTH-1:0] m_axi_wuser,

output wire [ M_COUNT-1:0] m_axi_wvalid,

input wire [ M_COUNT-1:0] m_axi_wready,

input wire [ M_COUNT*M_ID_WIDTH-1:0] m_axi_bid,

input wire [ M_COUNT*2-1:0] m_axi_bresp,

input wire [ M_COUNT*BUSER_WIDTH-1:0] m_axi_buser,

input wire [ M_COUNT-1:0] m_axi_bvalid,

output wire [ M_COUNT-1:0] m_axi_bready

github-actions · 2024-07-17T10:22:38Z

testbench/axi4_mux/axi_crossbar_wr.v

+parameter CL_S_COUNT = $clog2(S_COUNT);
+parameter CL_M_COUNT = $clog2(M_COUNT);
+parameter M_COUNT_P1 = M_COUNT+1;
+parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter CL_S_COUNT = $clog2(S_COUNT);

parameter CL_M_COUNT = $clog2(M_COUNT);

parameter M_COUNT_P1 = M_COUNT+1;

parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);

parameter CL_S_COUNT = $clog2(S_COUNT);

parameter CL_M_COUNT = $clog2(M_COUNT);

parameter M_COUNT_P1 = M_COUNT + 1;

parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);

github-actions · 2024-07-17T10:22:40Z

testbench/axi4_mux/axi_crossbar_wr.v

+        assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
+        assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;
+
+        assign s_cpl_id = m_axi_bid_mux;
+        assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;
+
+        // S side register
+        axi_register_wr #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(S_ID_WIDTH),
+            .AWUSER_ENABLE(AWUSER_ENABLE),
+            .AWUSER_WIDTH(AWUSER_WIDTH),
+            .WUSER_ENABLE(WUSER_ENABLE),
+            .WUSER_WIDTH(WUSER_WIDTH),
+            .BUSER_ENABLE(BUSER_ENABLE),
+            .BUSER_WIDTH(BUSER_WIDTH),
+            .AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),
+            .W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),
+            .B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .s_axi_awlen(s_axi_awlen[m*8 +: 8]),
+            .s_axi_awsize(s_axi_awsize[m*3 +: 3]),
+            .s_axi_awburst(s_axi_awburst[m*2 +: 2]),
+            .s_axi_awlock(s_axi_awlock[m]),
+            .s_axi_awcache(s_axi_awcache[m*4 +: 4]),
+            .s_axi_awprot(s_axi_awprot[m*3 +: 3]),
+            .s_axi_awqos(s_axi_awqos[m*4 +: 4]),
+            .s_axi_awregion(4'd0),
+            .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .s_axi_awvalid(s_axi_awvalid[m]),
+            .s_axi_awready(s_axi_awready[m]),
+            .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),
+            .s_axi_wlast(s_axi_wlast[m]),
+            .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),
+            .s_axi_wvalid(s_axi_wvalid[m]),
+            .s_axi_wready(s_axi_wready[m]),
+            .s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .s_axi_bresp(s_axi_bresp[m*2 +: 2]),
+            .s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]),
+            .s_axi_bvalid(s_axi_bvalid[m]),
+            .s_axi_bready(s_axi_bready[m]),
+            .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),
+            .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_awlen(int_s_axi_awlen[m*8 +: 8]),
+            .m_axi_awsize(int_s_axi_awsize[m*3 +: 3]),
+            .m_axi_awburst(int_s_axi_awburst[m*2 +: 2]),
+            .m_axi_awlock(int_s_axi_awlock[m]),
+            .m_axi_awcache(int_s_axi_awcache[m*4 +: 4]),
+            .m_axi_awprot(int_s_axi_awprot[m*3 +: 3]),
+            .m_axi_awqos(int_s_axi_awqos[m*4 +: 4]),
+            .m_axi_awregion(),
+            .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .m_axi_awvalid(int_s_axi_awvalid[m]),
+            .m_axi_awready(int_s_axi_awready[m]),
+            .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),
+            .m_axi_wlast(int_s_axi_wlast[m]),
+            .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),
+            .m_axi_wvalid(int_s_axi_wvalid[m]),
+            .m_axi_wready(int_s_axi_wready[m]),
+            .m_axi_bid(m_axi_bid_mux),
+            .m_axi_bresp(m_axi_bresp_mux),
+            .m_axi_buser(m_axi_buser_mux),
+            .m_axi_bvalid(m_axi_bvalid_mux),
+            .m_axi_bready(m_axi_bready_mux)
+        );
+    end // s_ifaces


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];

assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;

assign s_cpl_id = m_axi_bid_mux;

assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;

// S side register

axi_register_wr #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(S_ID_WIDTH),

.AWUSER_ENABLE(AWUSER_ENABLE),

.AWUSER_WIDTH(AWUSER_WIDTH),

.WUSER_ENABLE(WUSER_ENABLE),

.WUSER_WIDTH(WUSER_WIDTH),

.BUSER_ENABLE(BUSER_ENABLE),

.BUSER_WIDTH(BUSER_WIDTH),

.AW_REG_TYPE(S_AW_REG_TYPE[m*2 +: 2]),

.W_REG_TYPE(S_W_REG_TYPE[m*2 +: 2]),

.B_REG_TYPE(S_B_REG_TYPE[m*2 +: 2])

)

reg_inst (

.clk(clk),

.rst(rst),

.s_axi_awid(s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),

.s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),

.s_axi_awlen(s_axi_awlen[m*8 +: 8]),

.s_axi_awsize(s_axi_awsize[m*3 +: 3]),

.s_axi_awburst(s_axi_awburst[m*2 +: 2]),

.s_axi_awlock(s_axi_awlock[m]),

.s_axi_awcache(s_axi_awcache[m*4 +: 4]),

.s_axi_awprot(s_axi_awprot[m*3 +: 3]),

.s_axi_awqos(s_axi_awqos[m*4 +: 4]),

.s_axi_awregion(4'd0),

.s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),

.s_axi_awvalid(s_axi_awvalid[m]),

.s_axi_awready(s_axi_awready[m]),

.s_axi_wdata(s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),

.s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),

.s_axi_wlast(s_axi_wlast[m]),

.s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),

.s_axi_wvalid(s_axi_wvalid[m]),

.s_axi_wready(s_axi_wready[m]),

.s_axi_bid(s_axi_bid[m*S_ID_WIDTH +: S_ID_WIDTH]),

.s_axi_bresp(s_axi_bresp[m*2 +: 2]),

.s_axi_buser(s_axi_buser[m*BUSER_WIDTH +: BUSER_WIDTH]),

.s_axi_bvalid(s_axi_bvalid[m]),

.s_axi_bready(s_axi_bready[m]),

.m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH +: S_ID_WIDTH]),

.m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH +: ADDR_WIDTH]),

.m_axi_awlen(int_s_axi_awlen[m*8 +: 8]),

.m_axi_awsize(int_s_axi_awsize[m*3 +: 3]),

.m_axi_awburst(int_s_axi_awburst[m*2 +: 2]),

.m_axi_awlock(int_s_axi_awlock[m]),

.m_axi_awcache(int_s_axi_awcache[m*4 +: 4]),

.m_axi_awprot(int_s_axi_awprot[m*3 +: 3]),

.m_axi_awqos(int_s_axi_awqos[m*4 +: 4]),

.m_axi_awregion(),

.m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH +: AWUSER_WIDTH]),

.m_axi_awvalid(int_s_axi_awvalid[m]),

.m_axi_awready(int_s_axi_awready[m]),

.m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH +: DATA_WIDTH]),

.m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH +: STRB_WIDTH]),

.m_axi_wlast(int_s_axi_wlast[m]),

.m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH +: WUSER_WIDTH]),

.m_axi_wvalid(int_s_axi_wvalid[m]),

.m_axi_wready(int_s_axi_wready[m]),

.m_axi_bid(m_axi_bid_mux),

.m_axi_bresp(m_axi_bresp_mux),

.m_axi_buser(m_axi_buser_mux),

.m_axi_bvalid(m_axi_bvalid_mux),

.m_axi_bready(m_axi_bready_mux)

);

end // s_ifaces

w_select_reg <= w_select_next;

w_drop_reg <= w_drop_next;

end

github-actions · 2024-07-17T10:22:40Z

testbench/axi4_mux/axi_crossbar_wr.v

+    for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
+        // in-flight transaction count
+        wire trans_start;
+        wire trans_complete;
+        reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
+
+        wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
+
+        always @(posedge clk) begin
+            if (rst) begin
+                trans_count_reg <= 0;
+            end else begin
+                if (trans_start && !trans_complete) begin
+                    trans_count_reg <= trans_count_reg + 1;
+                end else if (!trans_start && trans_complete) begin
+                    trans_count_reg <= trans_count_reg - 1;
+                end
+            end
+        end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces

// in-flight transaction count

wire trans_start;

wire trans_complete;

reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;

wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;

always @(posedge clk) begin

if (rst) begin

trans_count_reg <= 0;

end else begin

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

end

end

// write data forwarding

assign int_axi_wvalid[m*M_COUNT +: M_COUNT] = (int_s_axi_wvalid[m] && w_select_valid_reg && !w_drop_reg) << w_select_reg;

assign int_s_axi_wready[m] = int_axi_wready[w_select_reg*S_COUNT+m] || w_drop_reg;

// decode error handling

reg [S_ID_WIDTH-1:0] decerr_m_axi_bid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_bid_next;

reg decerr_m_axi_bvalid_reg = 1'b0, decerr_m_axi_bvalid_next;

wire decerr_m_axi_bready;

assign m_rc_ready = !decerr_m_axi_bvalid_reg;

always @* begin

decerr_m_axi_bid_next = decerr_m_axi_bid_reg;

decerr_m_axi_bvalid_next = decerr_m_axi_bvalid_reg;

github-actions · 2024-07-17T10:22:40Z

testbench/axi4_mux/axi_crossbar_wr.v

+        // address arbitration
+        reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next;
+        reg w_select_valid_reg = 1'b0, w_select_valid_next;
+        reg w_select_new_reg = 1'b0, w_select_new_next;
+
+        wire [S_COUNT-1:0] a_request;
+        wire [S_COUNT-1:0] a_acknowledge;
+        wire [S_COUNT-1:0] a_grant;
+        wire a_grant_valid;
+        wire [CL_S_COUNT-1:0] a_grant_encoded;
+
+        arbiter #(
+            .PORTS(S_COUNT),
+            .ARB_TYPE_ROUND_ROBIN(1),
+            .ARB_BLOCK(1),
+            .ARB_BLOCK_ACK(1),
+            .ARB_LSB_HIGH_PRIORITY(1)
+        )
+        a_arb_inst (
+            .clk(clk),
+            .rst(rst),
+            .request(a_request),
+            .acknowledge(a_acknowledge),
+            .grant(a_grant),
+            .grant_valid(a_grant_valid),
+            .grant_encoded(a_grant_encoded)
+        );
+
+        // address mux
+        wire [M_ID_WIDTH-1:0]   s_axi_awid_mux     = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
+        wire [ADDR_WIDTH-1:0]   s_axi_awaddr_mux   = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
+        wire [7:0]              s_axi_awlen_mux    = int_s_axi_awlen[a_grant_encoded*8 +: 8];
+        wire [2:0]              s_axi_awsize_mux   = int_s_axi_awsize[a_grant_encoded*3 +: 3];
+        wire [1:0]              s_axi_awburst_mux  = int_s_axi_awburst[a_grant_encoded*2 +: 2];
+        wire                    s_axi_awlock_mux   = int_s_axi_awlock[a_grant_encoded];
+        wire [3:0]              s_axi_awcache_mux  = int_s_axi_awcache[a_grant_encoded*4 +: 4];
+        wire [2:0]              s_axi_awprot_mux   = int_s_axi_awprot[a_grant_encoded*3 +: 3];
+        wire [3:0]              s_axi_awqos_mux    = int_s_axi_awqos[a_grant_encoded*4 +: 4];
+        wire [3:0]              s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4];
+        wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux   = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH];
+        wire                    s_axi_awvalid_mux  = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
+        wire                    s_axi_awready_mux;
+
+        assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded;
+
+        for (m = 0; m < S_COUNT; m = m + 1) begin
+            assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// address arbitration

reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next;

reg w_select_valid_reg = 1'b0, w_select_valid_next;

reg w_select_new_reg = 1'b0, w_select_new_next;

wire [S_COUNT-1:0] a_request;

wire [S_COUNT-1:0] a_acknowledge;

wire [S_COUNT-1:0] a_grant;

wire a_grant_valid;

wire [CL_S_COUNT-1:0] a_grant_encoded;

arbiter #(

.PORTS(S_COUNT),

.ARB_TYPE_ROUND_ROBIN(1),

.ARB_BLOCK(1),

.ARB_BLOCK_ACK(1),

.ARB_LSB_HIGH_PRIORITY(1)

)

a_arb_inst (

.clk(clk),

.rst(rst),

.request(a_request),

.acknowledge(a_acknowledge),

.grant(a_grant),

.grant_valid(a_grant_valid),

.grant_encoded(a_grant_encoded)

);

// address mux

wire [M_ID_WIDTH-1:0] s_axi_awid_mux = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);

wire [ADDR_WIDTH-1:0] s_axi_awaddr_mux = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];

wire [7:0] s_axi_awlen_mux = int_s_axi_awlen[a_grant_encoded*8 +: 8];

wire [2:0] s_axi_awsize_mux = int_s_axi_awsize[a_grant_encoded*3 +: 3];

wire [1:0] s_axi_awburst_mux = int_s_axi_awburst[a_grant_encoded*2 +: 2];

wire s_axi_awlock_mux = int_s_axi_awlock[a_grant_encoded];

wire [3:0] s_axi_awcache_mux = int_s_axi_awcache[a_grant_encoded*4 +: 4];

wire [2:0] s_axi_awprot_mux = int_s_axi_awprot[a_grant_encoded*3 +: 3];

wire [3:0] s_axi_awqos_mux = int_s_axi_awqos[a_grant_encoded*4 +: 4];

wire [3:0] s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4 +: 4];

wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH];

wire s_axi_awvalid_mux = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;

wire s_axi_awready_mux;

assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded;

for (m = 0; m < S_COUNT; m = m + 1) begin

assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;

assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;

if (decerr_m_axi_bvalid_reg) begin

if (decerr_m_axi_bready) begin

decerr_m_axi_bvalid_next = 1'b0;

end

end else if (m_rc_valid && m_rc_ready) begin

decerr_m_axi_bid_next = int_s_axi_awid[m*S_ID_WIDTH+:S_ID_WIDTH];

decerr_m_axi_bvalid_next = 1'b1;

github-actions · 2024-07-17T10:22:40Z

testbench/axi4_mux/axi_crossbar_wr.v

+            assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;
+            assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;
+        end
+


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

github-actions · 2024-07-17T10:22:40Z

testbench/axi4_mux/axi_crossbar_wr.v

+        assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid;
+
+        // write data mux
+        wire [DATA_WIDTH-1:0]  s_axi_wdata_mux   = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH];
+        wire [STRB_WIDTH-1:0]  s_axi_wstrb_mux   = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH];
+        wire                   s_axi_wlast_mux   = int_s_axi_wlast[w_select_reg];
+        wire [WUSER_WIDTH-1:0] s_axi_wuser_mux   = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH];
+        wire                   s_axi_wvalid_mux  = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg;
+        wire                   s_axi_wready_mux;
+
+        assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg;
+
+        // write data routing
+        always @* begin
+            w_select_next = w_select_reg;
+            w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux);
+            w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge;
+
+            if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin
+                w_select_next = a_grant_encoded;
+                w_select_valid_next = a_grant_valid;
+                w_select_new_next = 1'b0;
+            end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid;

// write data mux

wire [DATA_WIDTH-1:0] s_axi_wdata_mux = int_s_axi_wdata[w_select_reg*DATA_WIDTH +: DATA_WIDTH];

wire [STRB_WIDTH-1:0] s_axi_wstrb_mux = int_s_axi_wstrb[w_select_reg*STRB_WIDTH +: STRB_WIDTH];

wire s_axi_wlast_mux = int_s_axi_wlast[w_select_reg];

wire [WUSER_WIDTH-1:0] s_axi_wuser_mux = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH];

wire s_axi_wvalid_mux = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg;

wire s_axi_wready_mux;

assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg;

// write data routing

always @* begin

w_select_next = w_select_reg;

w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux);

w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge;

if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin

w_select_next = a_grant_encoded;

w_select_valid_next = a_grant_valid;

w_select_new_next = 1'b0;

end

always @(posedge clk) begin

if (rst) begin

decerr_m_axi_bvalid_reg <= 1'b0;

end else begin

decerr_m_axi_bvalid_reg <= decerr_m_axi_bvalid_next;

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T12:31:12Z

testbench/axi4_mux/axi_crossbar_wr.v

+        always @(posedge clk) begin
+            if (rst) begin
+                w_select_valid_reg <= 1'b0;
+                w_select_new_reg <= 1'b1;
+            end else begin
+                w_select_valid_reg <= w_select_valid_next;
+                w_select_new_reg <= w_select_new_next;
+            end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always @(posedge clk) begin

if (rst) begin

w_select_valid_reg <= 1'b0;

w_select_new_reg <= 1'b1;

end else begin

w_select_valid_reg <= w_select_valid_next;

w_select_new_reg <= w_select_new_next;

end

decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;

end

// write response arbitration

wire [M_COUNT_P1-1:0] b_request;

wire [M_COUNT_P1-1:0] b_acknowledge;

wire [M_COUNT_P1-1:0] b_grant;

wire b_grant_valid;

wire [CL_M_COUNT_P1-1:0] b_grant_encoded;

arbiter #(

.PORTS(M_COUNT_P1),

.ARB_TYPE_ROUND_ROBIN(1),

.ARB_BLOCK(1),

.ARB_BLOCK_ACK(1),

.ARB_LSB_HIGH_PRIORITY(1)

) b_arb_inst (

.clk(clk),

.rst(rst),

.request(b_request),

.acknowledge(b_acknowledge),

.grant(b_grant),

.grant_valid(b_grant_valid),

.grant_encoded(b_grant_encoded)

);

// write response mux

wire [S_ID_WIDTH-1:0] m_axi_bid_mux = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH;

wire [1:0] m_axi_bresp_mux = {2'b11, int_m_axi_bresp} >> b_grant_encoded * 2;

wire [BUSER_WIDTH-1:0] m_axi_buser_mux = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH;

wire m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid;

wire m_axi_bready_mux;

assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded;

assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1);

for (n = 0; n < M_COUNT; n = n + 1) begin

assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n];

assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux;

end

assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];

assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;

assign s_cpl_id = m_axi_bid_mux;

assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;

// S side register

axi_register_wr #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(S_ID_WIDTH),

.AWUSER_ENABLE(AWUSER_ENABLE),

.AWUSER_WIDTH(AWUSER_WIDTH),

.WUSER_ENABLE(WUSER_ENABLE),

.WUSER_WIDTH(WUSER_WIDTH),

.BUSER_ENABLE(BUSER_ENABLE),

.BUSER_WIDTH(BUSER_WIDTH),

.AW_REG_TYPE(S_AW_REG_TYPE[m*2+:2]),

.W_REG_TYPE(S_W_REG_TYPE[m*2+:2]),

.B_REG_TYPE(S_B_REG_TYPE[m*2+:2])

) reg_inst (

.clk(clk),

.rst(rst),

.s_axi_awid(s_axi_awid[m*S_ID_WIDTH+:S_ID_WIDTH]),

.s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH+:ADDR_WIDTH]),

.s_axi_awlen(s_axi_awlen[m*8+:8]),

.s_axi_awsize(s_axi_awsize[m*3+:3]),

.s_axi_awburst(s_axi_awburst[m*2+:2]),

.s_axi_awlock(s_axi_awlock[m]),

.s_axi_awcache(s_axi_awcache[m*4+:4]),

.s_axi_awprot(s_axi_awprot[m*3+:3]),

.s_axi_awqos(s_axi_awqos[m*4+:4]),

.s_axi_awregion(4'd0),

.s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH+:AWUSER_WIDTH]),

.s_axi_awvalid(s_axi_awvalid[m]),

.s_axi_awready(s_axi_awready[m]),

.s_axi_wdata(s_axi_wdata[m*DATA_WIDTH+:DATA_WIDTH]),

.s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH+:STRB_WIDTH]),

.s_axi_wlast(s_axi_wlast[m]),

.s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH+:WUSER_WIDTH]),

.s_axi_wvalid(s_axi_wvalid[m]),

.s_axi_wready(s_axi_wready[m]),

.s_axi_bid(s_axi_bid[m*S_ID_WIDTH+:S_ID_WIDTH]),

.s_axi_bresp(s_axi_bresp[m*2+:2]),

.s_axi_buser(s_axi_buser[m*BUSER_WIDTH+:BUSER_WIDTH]),

.s_axi_bvalid(s_axi_bvalid[m]),

.s_axi_bready(s_axi_bready[m]),

.m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH+:S_ID_WIDTH]),

.m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH+:ADDR_WIDTH]),

.m_axi_awlen(int_s_axi_awlen[m*8+:8]),

.m_axi_awsize(int_s_axi_awsize[m*3+:3]),

.m_axi_awburst(int_s_axi_awburst[m*2+:2]),

.m_axi_awlock(int_s_axi_awlock[m]),

.m_axi_awcache(int_s_axi_awcache[m*4+:4]),

.m_axi_awprot(int_s_axi_awprot[m*3+:3]),

.m_axi_awqos(int_s_axi_awqos[m*4+:4]),

.m_axi_awregion(),

.m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH+:AWUSER_WIDTH]),

.m_axi_awvalid(int_s_axi_awvalid[m]),

.m_axi_awready(int_s_axi_awready[m]),

.m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH+:DATA_WIDTH]),

.m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH+:STRB_WIDTH]),

.m_axi_wlast(int_s_axi_wlast[m]),

.m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH+:WUSER_WIDTH]),

.m_axi_wvalid(int_s_axi_wvalid[m]),

.m_axi_wready(int_s_axi_wready[m]),

.m_axi_bid(m_axi_bid_mux),

.m_axi_bresp(m_axi_bresp_mux),

.m_axi_buser(m_axi_buser_mux),

.m_axi_bvalid(m_axi_bvalid_mux),

.m_axi_bready(m_axi_bready_mux)

);

end // s_ifaces

github-actions · 2024-07-17T12:31:12Z

testbench/axi4_mux/axi_crossbar_wr.v

+                w_select_new_reg <= w_select_new_next;
+            end
+
+            w_select_reg <= w_select_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

w_select_reg <= w_select_next;

for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces

// in-flight transaction count

wire trans_start;

wire trans_complete;

reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;

wire trans_limit = trans_count_reg >= M_ISSUE[n*32+:32] && !trans_complete;

always @(posedge clk) begin

if (rst) begin

trans_count_reg <= 0;

end else begin

if (trans_start && !trans_complete) begin

trans_count_reg <= trans_count_reg + 1;

end else if (!trans_start && trans_complete) begin

trans_count_reg <= trans_count_reg - 1;

end

end

end

// address arbitration

reg [CL_S_COUNT-1:0] w_select_reg = 0, w_select_next;

reg w_select_valid_reg = 1'b0, w_select_valid_next;

reg w_select_new_reg = 1'b0, w_select_new_next;

wire [S_COUNT-1:0] a_request;

wire [S_COUNT-1:0] a_acknowledge;

wire [S_COUNT-1:0] a_grant;

wire a_grant_valid;

wire [CL_S_COUNT-1:0] a_grant_encoded;

arbiter #(

.PORTS(S_COUNT),

.ARB_TYPE_ROUND_ROBIN(1),

.ARB_BLOCK(1),

.ARB_BLOCK_ACK(1),

.ARB_LSB_HIGH_PRIORITY(1)

) a_arb_inst (

.clk(clk),

.rst(rst),

.request(a_request),

.acknowledge(a_acknowledge),

.grant(a_grant),

.grant_valid(a_grant_valid),

.grant_encoded(a_grant_encoded)

);

// address mux

wire [M_ID_WIDTH-1:0] s_axi_awid_mux = int_s_axi_awid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);

wire [ADDR_WIDTH-1:0] s_axi_awaddr_mux = int_s_axi_awaddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];

wire [7:0] s_axi_awlen_mux = int_s_axi_awlen[a_grant_encoded*8+:8];

wire [2:0] s_axi_awsize_mux = int_s_axi_awsize[a_grant_encoded*3+:3];

wire [1:0] s_axi_awburst_mux = int_s_axi_awburst[a_grant_encoded*2+:2];

wire s_axi_awlock_mux = int_s_axi_awlock[a_grant_encoded];

wire [3:0] s_axi_awcache_mux = int_s_axi_awcache[a_grant_encoded*4+:4];

wire [2:0] s_axi_awprot_mux = int_s_axi_awprot[a_grant_encoded*3+:3];

wire [3:0] s_axi_awqos_mux = int_s_axi_awqos[a_grant_encoded*4+:4];

wire [3:0] s_axi_awregion_mux = int_s_axi_awregion[a_grant_encoded*4+:4];

wire [AWUSER_WIDTH-1:0] s_axi_awuser_mux = int_s_axi_awuser[a_grant_encoded*AWUSER_WIDTH +: AWUSER_WIDTH];

wire s_axi_awvalid_mux = int_axi_awvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;

wire s_axi_awready_mux;

assign int_axi_awready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_awready_mux) << a_grant_encoded;

for (m = 0; m < S_COUNT; m = m + 1) begin

assign a_request[m] = int_axi_awvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit && !w_select_valid_next;

assign a_acknowledge[m] = a_grant[m] && int_axi_awvalid[m*M_COUNT+n] && s_axi_awready_mux;

end

assign trans_start = s_axi_awvalid_mux && s_axi_awready_mux && a_grant_valid;

// write data mux

wire [DATA_WIDTH-1:0] s_axi_wdata_mux = int_s_axi_wdata[w_select_reg*DATA_WIDTH+:DATA_WIDTH];

wire [STRB_WIDTH-1:0] s_axi_wstrb_mux = int_s_axi_wstrb[w_select_reg*STRB_WIDTH+:STRB_WIDTH];

wire s_axi_wlast_mux = int_s_axi_wlast[w_select_reg];

wire [WUSER_WIDTH-1:0] s_axi_wuser_mux = int_s_axi_wuser[w_select_reg*WUSER_WIDTH +: WUSER_WIDTH];

wire s_axi_wvalid_mux = int_axi_wvalid[w_select_reg*M_COUNT+n] && w_select_valid_reg;

wire s_axi_wready_mux;

assign int_axi_wready[n*S_COUNT +: S_COUNT] = (w_select_valid_reg && s_axi_wready_mux) << w_select_reg;

// write data routing

always @* begin

w_select_next = w_select_reg;

w_select_valid_next = w_select_valid_reg && !(s_axi_wvalid_mux && s_axi_wready_mux && s_axi_wlast_mux);

w_select_new_next = w_select_new_reg || !a_grant_valid || a_acknowledge;

if (a_grant_valid && !w_select_valid_reg && w_select_new_reg) begin

w_select_next = a_grant_encoded;

w_select_valid_next = a_grant_valid;

w_select_new_next = 1'b0;

end

end

always @(posedge clk) begin

if (rst) begin

w_select_valid_reg <= 1'b0;

w_select_new_reg <= 1'b1;

end else begin

w_select_valid_reg <= w_select_valid_next;

w_select_new_reg <= w_select_new_next;

github-actions · 2024-07-17T12:31:12Z

testbench/axi4_mux/axi_crossbar_wr.v

+        // write response forwarding
+        wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
+
+        assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select;
+        assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n];
+
+        assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n];
+
+        // M side register
+        axi_register_wr #(
+            .DATA_WIDTH(DATA_WIDTH),
+            .ADDR_WIDTH(ADDR_WIDTH),
+            .STRB_WIDTH(STRB_WIDTH),
+            .ID_WIDTH(M_ID_WIDTH),
+            .AWUSER_ENABLE(AWUSER_ENABLE),
+            .AWUSER_WIDTH(AWUSER_WIDTH),
+            .WUSER_ENABLE(WUSER_ENABLE),
+            .WUSER_WIDTH(WUSER_WIDTH),
+            .BUSER_ENABLE(BUSER_ENABLE),
+            .BUSER_WIDTH(BUSER_WIDTH),
+            .AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),
+            .W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),
+            .B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])
+        )
+        reg_inst (
+            .clk(clk),
+            .rst(rst),
+            .s_axi_awid(s_axi_awid_mux),
+            .s_axi_awaddr(s_axi_awaddr_mux),
+            .s_axi_awlen(s_axi_awlen_mux),
+            .s_axi_awsize(s_axi_awsize_mux),
+            .s_axi_awburst(s_axi_awburst_mux),
+            .s_axi_awlock(s_axi_awlock_mux),
+            .s_axi_awcache(s_axi_awcache_mux),
+            .s_axi_awprot(s_axi_awprot_mux),
+            .s_axi_awqos(s_axi_awqos_mux),
+            .s_axi_awregion(s_axi_awregion_mux),
+            .s_axi_awuser(s_axi_awuser_mux),
+            .s_axi_awvalid(s_axi_awvalid_mux),
+            .s_axi_awready(s_axi_awready_mux),
+            .s_axi_wdata(s_axi_wdata_mux),
+            .s_axi_wstrb(s_axi_wstrb_mux),
+            .s_axi_wlast(s_axi_wlast_mux),
+            .s_axi_wuser(s_axi_wuser_mux),
+            .s_axi_wvalid(s_axi_wvalid_mux),
+            .s_axi_wready(s_axi_wready_mux),
+            .s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .s_axi_bresp(int_m_axi_bresp[n*2 +: 2]),
+            .s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),
+            .s_axi_bvalid(int_m_axi_bvalid[n]),
+            .s_axi_bready(int_m_axi_bready[n]),
+            .m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
+            .m_axi_awlen(m_axi_awlen[n*8 +: 8]),
+            .m_axi_awsize(m_axi_awsize[n*3 +: 3]),
+            .m_axi_awburst(m_axi_awburst[n*2 +: 2]),
+            .m_axi_awlock(m_axi_awlock[n]),
+            .m_axi_awcache(m_axi_awcache[n*4 +: 4]),
+            .m_axi_awprot(m_axi_awprot[n*3 +: 3]),
+            .m_axi_awqos(m_axi_awqos[n*4 +: 4]),
+            .m_axi_awregion(m_axi_awregion[n*4 +: 4]),
+            .m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]),
+            .m_axi_awvalid(m_axi_awvalid[n]),
+            .m_axi_awready(m_axi_awready[n]),
+            .m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]),
+            .m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]),
+            .m_axi_wlast(m_axi_wlast[n]),
+            .m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]),
+            .m_axi_wvalid(m_axi_wvalid[n]),
+            .m_axi_wready(m_axi_wready[n]),
+            .m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),
+            .m_axi_bresp(m_axi_bresp[n*2 +: 2]),
+            .m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),
+            .m_axi_bvalid(m_axi_bvalid[n]),
+            .m_axi_bready(m_axi_bready[n])
+        );
+    end // m_ifaces
+
+endgenerate


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// write response forwarding

wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;

assign int_axi_bvalid[n*S_COUNT +: S_COUNT] = int_m_axi_bvalid[n] << b_select;

assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n];

assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n];

// M side register

axi_register_wr #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(M_ID_WIDTH),

.AWUSER_ENABLE(AWUSER_ENABLE),

.AWUSER_WIDTH(AWUSER_WIDTH),

.WUSER_ENABLE(WUSER_ENABLE),

.WUSER_WIDTH(WUSER_WIDTH),

.BUSER_ENABLE(BUSER_ENABLE),

.BUSER_WIDTH(BUSER_WIDTH),

.AW_REG_TYPE(M_AW_REG_TYPE[n*2 +: 2]),

.W_REG_TYPE(M_W_REG_TYPE[n*2 +: 2]),

.B_REG_TYPE(M_B_REG_TYPE[n*2 +: 2])

)

reg_inst (

.clk(clk),

.rst(rst),

.s_axi_awid(s_axi_awid_mux),

.s_axi_awaddr(s_axi_awaddr_mux),

.s_axi_awlen(s_axi_awlen_mux),

.s_axi_awsize(s_axi_awsize_mux),

.s_axi_awburst(s_axi_awburst_mux),

.s_axi_awlock(s_axi_awlock_mux),

.s_axi_awcache(s_axi_awcache_mux),

.s_axi_awprot(s_axi_awprot_mux),

.s_axi_awqos(s_axi_awqos_mux),

.s_axi_awregion(s_axi_awregion_mux),

.s_axi_awuser(s_axi_awuser_mux),

.s_axi_awvalid(s_axi_awvalid_mux),

.s_axi_awready(s_axi_awready_mux),

.s_axi_wdata(s_axi_wdata_mux),

.s_axi_wstrb(s_axi_wstrb_mux),

.s_axi_wlast(s_axi_wlast_mux),

.s_axi_wuser(s_axi_wuser_mux),

.s_axi_wvalid(s_axi_wvalid_mux),

.s_axi_wready(s_axi_wready_mux),

.s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.s_axi_bresp(int_m_axi_bresp[n*2 +: 2]),

.s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),

.s_axi_bvalid(int_m_axi_bvalid[n]),

.s_axi_bready(int_m_axi_bready[n]),

.m_axi_awid(m_axi_awid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH +: ADDR_WIDTH]),

.m_axi_awlen(m_axi_awlen[n*8 +: 8]),

.m_axi_awsize(m_axi_awsize[n*3 +: 3]),

.m_axi_awburst(m_axi_awburst[n*2 +: 2]),

.m_axi_awlock(m_axi_awlock[n]),

.m_axi_awcache(m_axi_awcache[n*4 +: 4]),

.m_axi_awprot(m_axi_awprot[n*3 +: 3]),

.m_axi_awqos(m_axi_awqos[n*4 +: 4]),

.m_axi_awregion(m_axi_awregion[n*4 +: 4]),

.m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH +: AWUSER_WIDTH]),

.m_axi_awvalid(m_axi_awvalid[n]),

.m_axi_awready(m_axi_awready[n]),

.m_axi_wdata(m_axi_wdata[n*DATA_WIDTH +: DATA_WIDTH]),

.m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH +: STRB_WIDTH]),

.m_axi_wlast(m_axi_wlast[n]),

.m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH +: WUSER_WIDTH]),

.m_axi_wvalid(m_axi_wvalid[n]),

.m_axi_wready(m_axi_wready[n]),

.m_axi_bid(m_axi_bid[n*M_ID_WIDTH +: M_ID_WIDTH]),

.m_axi_bresp(m_axi_bresp[n*2 +: 2]),

.m_axi_buser(m_axi_buser[n*BUSER_WIDTH +: BUSER_WIDTH]),

.m_axi_bvalid(m_axi_bvalid[n]),

.m_axi_bready(m_axi_bready[n])

);

end // m_ifaces

endgenerate

w_select_reg <= w_select_next;

end

// write response forwarding

wire [CL_S_COUNT-1:0] b_select = m_axi_bid[n*M_ID_WIDTH+:M_ID_WIDTH] >> S_ID_WIDTH;

assign int_axi_bvalid[n*S_COUNT+:S_COUNT] = int_m_axi_bvalid[n] << b_select;

assign int_m_axi_bready[n] = int_axi_bready[b_select*M_COUNT+n];

assign trans_complete = int_m_axi_bvalid[n] && int_m_axi_bready[n];

// M side register

axi_register_wr #(

.DATA_WIDTH(DATA_WIDTH),

.ADDR_WIDTH(ADDR_WIDTH),

.STRB_WIDTH(STRB_WIDTH),

.ID_WIDTH(M_ID_WIDTH),

.AWUSER_ENABLE(AWUSER_ENABLE),

.AWUSER_WIDTH(AWUSER_WIDTH),

.WUSER_ENABLE(WUSER_ENABLE),

.WUSER_WIDTH(WUSER_WIDTH),

.BUSER_ENABLE(BUSER_ENABLE),

.BUSER_WIDTH(BUSER_WIDTH),

.AW_REG_TYPE(M_AW_REG_TYPE[n*2+:2]),

.W_REG_TYPE(M_W_REG_TYPE[n*2+:2]),

.B_REG_TYPE(M_B_REG_TYPE[n*2+:2])

) reg_inst (

.clk(clk),

.rst(rst),

.s_axi_awid(s_axi_awid_mux),

.s_axi_awaddr(s_axi_awaddr_mux),

.s_axi_awlen(s_axi_awlen_mux),

.s_axi_awsize(s_axi_awsize_mux),

.s_axi_awburst(s_axi_awburst_mux),

.s_axi_awlock(s_axi_awlock_mux),

.s_axi_awcache(s_axi_awcache_mux),

.s_axi_awprot(s_axi_awprot_mux),

.s_axi_awqos(s_axi_awqos_mux),

.s_axi_awregion(s_axi_awregion_mux),

.s_axi_awuser(s_axi_awuser_mux),

.s_axi_awvalid(s_axi_awvalid_mux),

.s_axi_awready(s_axi_awready_mux),

.s_axi_wdata(s_axi_wdata_mux),

.s_axi_wstrb(s_axi_wstrb_mux),

.s_axi_wlast(s_axi_wlast_mux),

.s_axi_wuser(s_axi_wuser_mux),

.s_axi_wvalid(s_axi_wvalid_mux),

.s_axi_wready(s_axi_wready_mux),

.s_axi_bid(int_m_axi_bid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.s_axi_bresp(int_m_axi_bresp[n*2+:2]),

.s_axi_buser(int_m_axi_buser[n*BUSER_WIDTH+:BUSER_WIDTH]),

.s_axi_bvalid(int_m_axi_bvalid[n]),

.s_axi_bready(int_m_axi_bready[n]),

.m_axi_awid(m_axi_awid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.m_axi_awaddr(m_axi_awaddr[n*ADDR_WIDTH+:ADDR_WIDTH]),

.m_axi_awlen(m_axi_awlen[n*8+:8]),

.m_axi_awsize(m_axi_awsize[n*3+:3]),

.m_axi_awburst(m_axi_awburst[n*2+:2]),

.m_axi_awlock(m_axi_awlock[n]),

.m_axi_awcache(m_axi_awcache[n*4+:4]),

.m_axi_awprot(m_axi_awprot[n*3+:3]),

.m_axi_awqos(m_axi_awqos[n*4+:4]),

.m_axi_awregion(m_axi_awregion[n*4+:4]),

.m_axi_awuser(m_axi_awuser[n*AWUSER_WIDTH+:AWUSER_WIDTH]),

.m_axi_awvalid(m_axi_awvalid[n]),

.m_axi_awready(m_axi_awready[n]),

.m_axi_wdata(m_axi_wdata[n*DATA_WIDTH+:DATA_WIDTH]),

.m_axi_wstrb(m_axi_wstrb[n*STRB_WIDTH+:STRB_WIDTH]),

.m_axi_wlast(m_axi_wlast[n]),

.m_axi_wuser(m_axi_wuser[n*WUSER_WIDTH+:WUSER_WIDTH]),

.m_axi_wvalid(m_axi_wvalid[n]),

.m_axi_wready(m_axi_wready[n]),

.m_axi_bid(m_axi_bid[n*M_ID_WIDTH+:M_ID_WIDTH]),

.m_axi_bresp(m_axi_bresp[n*2+:2]),

.m_axi_buser(m_axi_buser[n*BUSER_WIDTH+:BUSER_WIDTH]),

.m_axi_bvalid(m_axi_bvalid[n]),

.m_axi_bready(m_axi_bready[n])

);

end // m_ifaces

endgenerate

github-actions · 2024-07-17T12:31:12Z

testbench/axi4_mux/axi_crossbar_wrap_2x1.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-17T12:31:12Z

testbench/axi4_mux/axi_crossbar_wrap_2x1.v

+module axi_crossbar_wrap_2x1 #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module axi_crossbar_wrap_2x1 #

(

module axi_crossbar_wrap_2x1 #(

github-actions · 2024-07-17T12:31:15Z

testbench/axi4_mux/axi_register_rd.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-17T12:31:15Z

testbench/axi4_mux/axi_register_rd.v

+module axi_register_rd #
+(


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

module axi_register_rd #

(

module axi_register_rd #(

github-actions · 2024-07-17T12:31:15Z

testbench/axi4_mux/axi_register_rd.v

+    // Width of address bus in bits
+    parameter ADDR_WIDTH = 32,
+    // Width of wstrb (width of data bus in words)
+    parameter STRB_WIDTH = (DATA_WIDTH/8),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter STRB_WIDTH = (DATA_WIDTH/8),

parameter STRB_WIDTH = (DATA_WIDTH / 8),

github-actions · 2024-07-17T12:31:15Z

testbench/axi4_mux/axi_register_rd.v

+)
+(
+    input  wire                     clk,
+    input  wire                     rst,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

)

(

input wire clk,

input wire rst,

) (

input wire clk,

input wire rst,

github-actions · 2024-07-17T12:31:15Z

testbench/axi4_mux/axi_register_rd.v

+    input  wire [ID_WIDTH-1:0]      s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]    s_axi_araddr,
+    input  wire [7:0]               s_axi_arlen,
+    input  wire [2:0]               s_axi_arsize,
+    input  wire [1:0]               s_axi_arburst,
+    input  wire                     s_axi_arlock,
+    input  wire [3:0]               s_axi_arcache,
+    input  wire [2:0]               s_axi_arprot,
+    input  wire [3:0]               s_axi_arqos,
+    input  wire [3:0]               s_axi_arregion,
+    input  wire [ARUSER_WIDTH-1:0]  s_axi_aruser,
+    input  wire                     s_axi_arvalid,
+    output wire                     s_axi_arready,
+    output wire [ID_WIDTH-1:0]      s_axi_rid,
+    output wire [DATA_WIDTH-1:0]    s_axi_rdata,
+    output wire [1:0]               s_axi_rresp,
+    output wire                     s_axi_rlast,
+    output wire [RUSER_WIDTH-1:0]   s_axi_ruser,
+    output wire                     s_axi_rvalid,
+    input  wire                     s_axi_rready,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input wire [ID_WIDTH-1:0] s_axi_arid,

input wire [ADDR_WIDTH-1:0] s_axi_araddr,

input wire [7:0] s_axi_arlen,

input wire [2:0] s_axi_arsize,

input wire [1:0] s_axi_arburst,

input wire s_axi_arlock,

input wire [3:0] s_axi_arcache,

input wire [2:0] s_axi_arprot,

input wire [3:0] s_axi_arqos,

input wire [3:0] s_axi_arregion,

input wire [ARUSER_WIDTH-1:0] s_axi_aruser,

input wire s_axi_arvalid,

output wire s_axi_arready,

output wire [ID_WIDTH-1:0] s_axi_rid,

output wire [DATA_WIDTH-1:0] s_axi_rdata,

output wire [1:0] s_axi_rresp,

output wire s_axi_rlast,

output wire [RUSER_WIDTH-1:0] s_axi_ruser,

output wire s_axi_rvalid,

input wire s_axi_rready,

input wire [ ID_WIDTH-1:0] s_axi_arid,

input wire [ ADDR_WIDTH-1:0] s_axi_araddr,

input wire [ 7:0] s_axi_arlen,

input wire [ 2:0] s_axi_arsize,

input wire [ 1:0] s_axi_arburst,

input wire s_axi_arlock,

input wire [ 3:0] s_axi_arcache,

input wire [ 2:0] s_axi_arprot,

input wire [ 3:0] s_axi_arqos,

input wire [ 3:0] s_axi_arregion,

input wire [ARUSER_WIDTH-1:0] s_axi_aruser,

input wire s_axi_arvalid,

output wire s_axi_arready,

output wire [ ID_WIDTH-1:0] s_axi_rid,

output wire [ DATA_WIDTH-1:0] s_axi_rdata,

output wire [ 1:0] s_axi_rresp,

output wire s_axi_rlast,

output wire [ RUSER_WIDTH-1:0] s_axi_ruser,

output wire s_axi_rvalid,

input wire s_axi_rready,

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T14:00:51Z

testbench/axi4_mux/axi_register_rd.v

+    output wire [ID_WIDTH-1:0]      m_axi_arid,
+    output wire [ADDR_WIDTH-1:0]    m_axi_araddr,
+    output wire [7:0]               m_axi_arlen,
+    output wire [2:0]               m_axi_arsize,
+    output wire [1:0]               m_axi_arburst,
+    output wire                     m_axi_arlock,
+    output wire [3:0]               m_axi_arcache,
+    output wire [2:0]               m_axi_arprot,
+    output wire [3:0]               m_axi_arqos,
+    output wire [3:0]               m_axi_arregion,
+    output wire [ARUSER_WIDTH-1:0]  m_axi_aruser,
+    output wire                     m_axi_arvalid,
+    input  wire                     m_axi_arready,
+    input  wire [ID_WIDTH-1:0]      m_axi_rid,
+    input  wire [DATA_WIDTH-1:0]    m_axi_rdata,
+    input  wire [1:0]               m_axi_rresp,
+    input  wire                     m_axi_rlast,
+    input  wire [RUSER_WIDTH-1:0]   m_axi_ruser,
+    input  wire                     m_axi_rvalid,
+    output wire                     m_axi_rready


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output wire [ID_WIDTH-1:0] m_axi_arid,

output wire [ADDR_WIDTH-1:0] m_axi_araddr,

output wire [7:0] m_axi_arlen,

output wire [2:0] m_axi_arsize,

output wire [1:0] m_axi_arburst,

output wire m_axi_arlock,

output wire [3:0] m_axi_arcache,

output wire [2:0] m_axi_arprot,

output wire [3:0] m_axi_arqos,

output wire [3:0] m_axi_arregion,

output wire [ARUSER_WIDTH-1:0] m_axi_aruser,

output wire m_axi_arvalid,

input wire m_axi_arready,

input wire [ID_WIDTH-1:0] m_axi_rid,

input wire [DATA_WIDTH-1:0] m_axi_rdata,

input wire [1:0] m_axi_rresp,

input wire m_axi_rlast,

input wire [RUSER_WIDTH-1:0] m_axi_ruser,

input wire m_axi_rvalid,

output wire m_axi_rready

output wire [ ID_WIDTH-1:0] m_axi_arid,

output wire [ ADDR_WIDTH-1:0] m_axi_araddr,

output wire [ 7:0] m_axi_arlen,

output wire [ 2:0] m_axi_arsize,

output wire [ 1:0] m_axi_arburst,

output wire m_axi_arlock,

output wire [ 3:0] m_axi_arcache,

output wire [ 2:0] m_axi_arprot,

output wire [ 3:0] m_axi_arqos,

output wire [ 3:0] m_axi_arregion,

output wire [ARUSER_WIDTH-1:0] m_axi_aruser,

output wire m_axi_arvalid,

input wire m_axi_arready,

input wire [ ID_WIDTH-1:0] m_axi_rid,

input wire [ DATA_WIDTH-1:0] m_axi_rdata,

input wire [ 1:0] m_axi_rresp,

input wire m_axi_rlast,

input wire [ RUSER_WIDTH-1:0] m_axi_ruser,

input wire m_axi_rvalid,

output wire m_axi_rready

github-actions · 2024-07-17T14:00:51Z

testbench/axi4_mux/axi_register_rd.v

+generate
+
+// AR channel
+
+if (AR_REG_TYPE > 1) begin
+// skid buffer, no bubble cycles
+
+// datapath registers
+reg                    s_axi_arready_reg = 1'b0;
+
+reg [ID_WIDTH-1:0]     m_axi_arid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   m_axi_araddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              m_axi_arlen_reg    = 8'd0;
+reg [2:0]              m_axi_arsize_reg   = 3'd0;
+reg [1:0]              m_axi_arburst_reg  = 2'd0;
+reg                    m_axi_arlock_reg   = 1'b0;
+reg [3:0]              m_axi_arcache_reg  = 4'd0;
+reg [2:0]              m_axi_arprot_reg   = 3'd0;
+reg [3:0]              m_axi_arqos_reg    = 4'd0;
+reg [3:0]              m_axi_arregion_reg = 4'd0;
+reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg   = {ARUSER_WIDTH{1'b0}};
+reg                    m_axi_arvalid_reg  = 1'b0, m_axi_arvalid_next;
+
+reg [ID_WIDTH-1:0]     temp_m_axi_arid_reg     = {ID_WIDTH{1'b0}};
+reg [ADDR_WIDTH-1:0]   temp_m_axi_araddr_reg   = {ADDR_WIDTH{1'b0}};
+reg [7:0]              temp_m_axi_arlen_reg    = 8'd0;
+reg [2:0]              temp_m_axi_arsize_reg   = 3'd0;
+reg [1:0]              temp_m_axi_arburst_reg  = 2'd0;
+reg                    temp_m_axi_arlock_reg   = 1'b0;
+reg [3:0]              temp_m_axi_arcache_reg  = 4'd0;
+reg [2:0]              temp_m_axi_arprot_reg   = 3'd0;
+reg [3:0]              temp_m_axi_arqos_reg    = 4'd0;
+reg [3:0]              temp_m_axi_arregion_reg = 4'd0;
+reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg   = {ARUSER_WIDTH{1'b0}};
+reg                    temp_m_axi_arvalid_reg  = 1'b0, temp_m_axi_arvalid_next;
+
+// datapath control
+reg store_axi_ar_input_to_output;
+reg store_axi_ar_input_to_temp;
+reg store_axi_ar_temp_to_output;
+
+assign s_axi_arready  = s_axi_arready_reg;
+
+assign m_axi_arid     = m_axi_arid_reg;
+assign m_axi_araddr   = m_axi_araddr_reg;
+assign m_axi_arlen    = m_axi_arlen_reg;
+assign m_axi_arsize   = m_axi_arsize_reg;
+assign m_axi_arburst  = m_axi_arburst_reg;
+assign m_axi_arlock   = m_axi_arlock_reg;
+assign m_axi_arcache  = m_axi_arcache_reg;
+assign m_axi_arprot   = m_axi_arprot_reg;
+assign m_axi_arqos    = m_axi_arqos_reg;
+assign m_axi_arregion = m_axi_arregion_reg;
+assign m_axi_aruser   = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};
+assign m_axi_arvalid  = m_axi_arvalid_reg;
+
+// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid));
+
+always @* begin
+    // transfer sink ready state to source
+    m_axi_arvalid_next = m_axi_arvalid_reg;
+    temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;
+
+    store_axi_ar_input_to_output = 1'b0;
+    store_axi_ar_input_to_temp = 1'b0;
+    store_axi_ar_temp_to_output = 1'b0;
+
+    if (s_axi_arready_reg) begin
+        // input is ready
+        if (m_axi_arready | ~m_axi_arvalid_reg) begin


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

generate

// AR channel

if (AR_REG_TYPE > 1) begin

// skid buffer, no bubble cycles

// datapath registers

reg s_axi_arready_reg = 1'b0;

reg [ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}};

reg [ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};

reg [7:0] m_axi_arlen_reg = 8'd0;

reg [2:0] m_axi_arsize_reg = 3'd0;

reg [1:0] m_axi_arburst_reg = 2'd0;

reg m_axi_arlock_reg = 1'b0;

reg [3:0] m_axi_arcache_reg = 4'd0;

reg [2:0] m_axi_arprot_reg = 3'd0;

reg [3:0] m_axi_arqos_reg = 4'd0;

reg [3:0] m_axi_arregion_reg = 4'd0;

reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};

reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;

reg [ID_WIDTH-1:0] temp_m_axi_arid_reg = {ID_WIDTH{1'b0}};

reg [ADDR_WIDTH-1:0] temp_m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};

reg [7:0] temp_m_axi_arlen_reg = 8'd0;

reg [2:0] temp_m_axi_arsize_reg = 3'd0;

reg [1:0] temp_m_axi_arburst_reg = 2'd0;

reg temp_m_axi_arlock_reg = 1'b0;

reg [3:0] temp_m_axi_arcache_reg = 4'd0;

reg [2:0] temp_m_axi_arprot_reg = 3'd0;

reg [3:0] temp_m_axi_arqos_reg = 4'd0;

reg [3:0] temp_m_axi_arregion_reg = 4'd0;

reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};

reg temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;

// datapath control

reg store_axi_ar_input_to_output;

reg store_axi_ar_input_to_temp;

reg store_axi_ar_temp_to_output;

assign s_axi_arready = s_axi_arready_reg;

assign m_axi_arid = m_axi_arid_reg;

assign m_axi_araddr = m_axi_araddr_reg;

assign m_axi_arlen = m_axi_arlen_reg;

assign m_axi_arsize = m_axi_arsize_reg;

assign m_axi_arburst = m_axi_arburst_reg;

assign m_axi_arlock = m_axi_arlock_reg;

assign m_axi_arcache = m_axi_arcache_reg;

assign m_axi_arprot = m_axi_arprot_reg;

assign m_axi_arqos = m_axi_arqos_reg;

assign m_axi_arregion = m_axi_arregion_reg;

assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};

assign m_axi_arvalid = m_axi_arvalid_reg;

// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)

wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid));

always @* begin

// transfer sink ready state to source

m_axi_arvalid_next = m_axi_arvalid_reg;

temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;

store_axi_ar_input_to_output = 1'b0;

store_axi_ar_input_to_temp = 1'b0;

store_axi_ar_temp_to_output = 1'b0;

if (s_axi_arready_reg) begin

// input is ready

if (m_axi_arready | ~m_axi_arvalid_reg) begin

generate

// AR channel

if (AR_REG_TYPE > 1) begin

// skid buffer, no bubble cycles

// datapath registers

reg s_axi_arready_reg = 1'b0;

reg [ ID_WIDTH-1:0] m_axi_arid_reg = {ID_WIDTH{1'b0}};

reg [ ADDR_WIDTH-1:0] m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};

reg [ 7:0] m_axi_arlen_reg = 8'd0;

reg [ 2:0] m_axi_arsize_reg = 3'd0;

reg [ 1:0] m_axi_arburst_reg = 2'd0;

reg m_axi_arlock_reg = 1'b0;

reg [ 3:0] m_axi_arcache_reg = 4'd0;

reg [ 2:0] m_axi_arprot_reg = 3'd0;

reg [ 3:0] m_axi_arqos_reg = 4'd0;

reg [ 3:0] m_axi_arregion_reg = 4'd0;

reg [ARUSER_WIDTH-1:0] m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};

reg m_axi_arvalid_reg = 1'b0, m_axi_arvalid_next;

reg [ ID_WIDTH-1:0] temp_m_axi_arid_reg = {ID_WIDTH{1'b0}};

reg [ ADDR_WIDTH-1:0] temp_m_axi_araddr_reg = {ADDR_WIDTH{1'b0}};

reg [ 7:0] temp_m_axi_arlen_reg = 8'd0;

reg [ 2:0] temp_m_axi_arsize_reg = 3'd0;

reg [ 1:0] temp_m_axi_arburst_reg = 2'd0;

reg temp_m_axi_arlock_reg = 1'b0;

reg [ 3:0] temp_m_axi_arcache_reg = 4'd0;

reg [ 2:0] temp_m_axi_arprot_reg = 3'd0;

reg [ 3:0] temp_m_axi_arqos_reg = 4'd0;

reg [ 3:0] temp_m_axi_arregion_reg = 4'd0;

reg [ARUSER_WIDTH-1:0] temp_m_axi_aruser_reg = {ARUSER_WIDTH{1'b0}};

reg temp_m_axi_arvalid_reg = 1'b0, temp_m_axi_arvalid_next;

// datapath control

reg store_axi_ar_input_to_output;

reg store_axi_ar_input_to_temp;

reg store_axi_ar_temp_to_output;

assign s_axi_arready = s_axi_arready_reg;

assign m_axi_arid = m_axi_arid_reg;

assign m_axi_araddr = m_axi_araddr_reg;

assign m_axi_arlen = m_axi_arlen_reg;

assign m_axi_arsize = m_axi_arsize_reg;

assign m_axi_arburst = m_axi_arburst_reg;

assign m_axi_arlock = m_axi_arlock_reg;

assign m_axi_arcache = m_axi_arcache_reg;

assign m_axi_arprot = m_axi_arprot_reg;

assign m_axi_arqos = m_axi_arqos_reg;

assign m_axi_arregion = m_axi_arregion_reg;

assign m_axi_aruser = ARUSER_ENABLE ? m_axi_aruser_reg : {ARUSER_WIDTH{1'b0}};

assign m_axi_arvalid = m_axi_arvalid_reg;

// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)

wire s_axi_arready_early = m_axi_arready | (~temp_m_axi_arvalid_reg & (~m_axi_arvalid_reg | ~s_axi_arvalid));

always @* begin

// transfer sink ready state to source

m_axi_arvalid_next = m_axi_arvalid_reg;

temp_m_axi_arvalid_next = temp_m_axi_arvalid_reg;

store_axi_ar_input_to_output = 1'b0;

store_axi_ar_input_to_temp = 1'b0;

store_axi_ar_temp_to_output = 1'b0;

if (s_axi_arready_reg) begin

// input is ready

if (m_axi_arready | ~m_axi_arvalid_reg) begin

github-actions · 2024-07-17T14:00:52Z

testbench/axi4_mux/axi_register_rd.v

+            // output is ready or currently not valid, transfer data to output
+            m_axi_arvalid_next = s_axi_arvalid;
+            store_axi_ar_input_to_output = 1'b1;
+        end else begin


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else begin

end else begin

github-actions · 2024-07-17T14:00:52Z

testbench/axi4_mux/axi_register_rd.v

+            // output is not ready, store input in temp
+            temp_m_axi_arvalid_next = s_axi_arvalid;
+            store_axi_ar_input_to_temp = 1'b1;
+        end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

end else if (m_axi_arready) begin

// input is not ready, but output is ready

m_axi_arvalid_next = temp_m_axi_arvalid_reg;

temp_m_axi_arvalid_next = 1'b0;

store_axi_ar_temp_to_output = 1'b1;

end

github-actions · 2024-07-17T14:00:52Z

testbench/axi4_mux/axi_register_rd.v

+    end else if (m_axi_arready) begin
+        // input is not ready, but output is ready
+        m_axi_arvalid_next = temp_m_axi_arvalid_reg;
+        temp_m_axi_arvalid_next = 1'b0;
+        store_axi_ar_temp_to_output = 1'b1;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else if (m_axi_arready) begin

// input is not ready, but output is ready

m_axi_arvalid_next = temp_m_axi_arvalid_reg;

temp_m_axi_arvalid_next = 1'b0;

store_axi_ar_temp_to_output = 1'b1;

end

end

end

github-actions · 2024-07-17T14:00:55Z

testbench/axi4_mux/axi_register_rd.v

+always @* begin
+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always @* begin

// transfer sink ready state to source

s_axi_rvalid_next = s_axi_rvalid_reg;

always @* begin

// transfer sink ready state to source

s_axi_rvalid_next = s_axi_rvalid_reg;

github-actions · 2024-07-17T14:00:55Z

testbench/axi4_mux/axi_register_rd.v

+    // transfer sink ready state to source
+    s_axi_rvalid_next = s_axi_rvalid_reg;
+
+    store_axi_r_input_to_output = 1'b0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

store_axi_r_input_to_output = 1'b0;

store_axi_r_input_to_output = 1'b0;

github-actions · 2024-07-17T14:00:55Z

testbench/axi4_mux/axi_register_rd.v

+    if (m_axi_rready_reg) begin
+        s_axi_rvalid_next = m_axi_rvalid;
+        store_axi_r_input_to_output = 1'b1;
+    end else if (s_axi_rready) begin
+        s_axi_rvalid_next = 1'b0;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (m_axi_rready_reg) begin

s_axi_rvalid_next = m_axi_rvalid;

store_axi_r_input_to_output = 1'b1;

end else if (s_axi_rready) begin

s_axi_rvalid_next = 1'b0;

end

end

if (m_axi_rready_reg) begin

s_axi_rvalid_next = m_axi_rvalid;

store_axi_r_input_to_output = 1'b1;

end else if (s_axi_rready) begin

s_axi_rvalid_next = 1'b0;

end

end

github-actions · 2024-07-17T14:00:55Z

testbench/axi4_mux/axi_register_rd.v

+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_rready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+    end else begin
+        m_axi_rready_reg <= m_axi_rready_early;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always @(posedge clk) begin

if (rst) begin

m_axi_rready_reg <= 1'b0;

s_axi_rvalid_reg <= 1'b0;

end else begin

m_axi_rready_reg <= m_axi_rready_early;

s_axi_rvalid_reg <= s_axi_rvalid_next;

end

always @(posedge clk) begin

if (rst) begin

m_axi_rready_reg <= 1'b0;

s_axi_rvalid_reg <= 1'b0;

end else begin

m_axi_rready_reg <= m_axi_rready_early;

s_axi_rvalid_reg <= s_axi_rvalid_next;

end

github-actions · 2024-07-17T14:00:55Z

testbench/axi4_mux/axi_register_rd.v

+    // datapath
+    if (store_axi_r_input_to_output) begin
+        s_axi_rid_reg   <= m_axi_rid;
+        s_axi_rdata_reg <= m_axi_rdata;
+        s_axi_rresp_reg <= m_axi_rresp;
+        s_axi_rlast_reg <= m_axi_rlast;
+        s_axi_ruser_reg <= m_axi_ruser;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath

if (store_axi_r_input_to_output) begin

s_axi_rid_reg <= m_axi_rid;

s_axi_rdata_reg <= m_axi_rdata;

s_axi_rresp_reg <= m_axi_rresp;

s_axi_rlast_reg <= m_axi_rlast;

s_axi_ruser_reg <= m_axi_ruser;

end

end

// datapath

if (store_axi_r_input_to_output) begin

s_axi_rid_reg <= m_axi_rid;

s_axi_rdata_reg <= m_axi_rdata;

s_axi_rresp_reg <= m_axi_rresp;

s_axi_rlast_reg <= m_axi_rlast;

s_axi_ruser_reg <= m_axi_ruser;

end

end

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T14:13:43Z

testbench/axi4_mux/axi_register_rd.v

+    end
+end
+
+end else begin


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else begin

end else begin

github-actions · 2024-07-17T14:13:43Z

testbench/axi4_mux/axi_register_rd.v

+    // bypass R channel
+    assign s_axi_rid = m_axi_rid;
+    assign s_axi_rdata = m_axi_rdata;
+    assign s_axi_rresp = m_axi_rresp;
+    assign s_axi_rlast = m_axi_rlast;
+    assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}};
+    assign s_axi_rvalid = m_axi_rvalid;
+    assign m_axi_rready = s_axi_rready;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// bypass R channel

assign s_axi_rid = m_axi_rid;

assign s_axi_rdata = m_axi_rdata;

assign s_axi_rresp = m_axi_rresp;

assign s_axi_rlast = m_axi_rlast;

assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}};

assign s_axi_rvalid = m_axi_rvalid;

assign m_axi_rready = s_axi_rready;

// bypass R channel

assign s_axi_rid = m_axi_rid;

assign s_axi_rdata = m_axi_rdata;

assign s_axi_rresp = m_axi_rresp;

assign s_axi_rlast = m_axi_rlast;

assign s_axi_ruser = RUSER_ENABLE ? m_axi_ruser : {RUSER_WIDTH{1'b0}};

assign s_axi_rvalid = m_axi_rvalid;

assign m_axi_rready = s_axi_rready;

github-actions · 2024-07-17T14:13:43Z

testbench/axi4_mux/axi_register_rd.v

+    assign s_axi_rvalid = m_axi_rvalid;
+    assign m_axi_rready = s_axi_rready;
+
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

github-actions · 2024-07-17T14:13:44Z

testbench/axi4_mux/axi_register_rd.v

+
+end
+
+endgenerate


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endgenerate

endgenerate

github-actions · 2024-07-17T14:13:44Z

testbench/axi4_mux/axi_register_wr.v

+`resetall
+`timescale 1ns / 1ps
+`default_nettype none


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

`resetall

`timescale 1ns / 1ps

`default_nettype none

`resetall `timescale 1ns / 1ps `default_nettype none

github-actions · 2024-07-17T14:13:46Z

testbench/axi4_mux/axi_register_wr.v

+    // datapath
+    if (store_axi_w_input_to_output) begin
+        m_axi_wdata_reg <= s_axi_wdata;
+        m_axi_wstrb_reg <= s_axi_wstrb;
+        m_axi_wlast_reg <= s_axi_wlast;
+        m_axi_wuser_reg <= s_axi_wuser;
+    end else if (store_axi_w_temp_to_output) begin
+        m_axi_wdata_reg <= temp_m_axi_wdata_reg;
+        m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;
+        m_axi_wlast_reg <= temp_m_axi_wlast_reg;
+        m_axi_wuser_reg <= temp_m_axi_wuser_reg;
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath

if (store_axi_w_input_to_output) begin

m_axi_wdata_reg <= s_axi_wdata;

m_axi_wstrb_reg <= s_axi_wstrb;

m_axi_wlast_reg <= s_axi_wlast;

m_axi_wuser_reg <= s_axi_wuser;

end else if (store_axi_w_temp_to_output) begin

m_axi_wdata_reg <= temp_m_axi_wdata_reg;

m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;

m_axi_wlast_reg <= temp_m_axi_wlast_reg;

m_axi_wuser_reg <= temp_m_axi_wuser_reg;

end

// datapath

if (store_axi_w_input_to_output) begin

m_axi_wdata_reg <= s_axi_wdata;

m_axi_wstrb_reg <= s_axi_wstrb;

m_axi_wlast_reg <= s_axi_wlast;

m_axi_wuser_reg <= s_axi_wuser;

end else if (store_axi_w_temp_to_output) begin

m_axi_wdata_reg <= temp_m_axi_wdata_reg;

m_axi_wstrb_reg <= temp_m_axi_wstrb_reg;

m_axi_wlast_reg <= temp_m_axi_wlast_reg;

m_axi_wuser_reg <= temp_m_axi_wuser_reg;

end

github-actions · 2024-07-17T14:13:46Z

testbench/axi4_mux/axi_register_wr.v

+    if (store_axi_w_input_to_temp) begin
+        temp_m_axi_wdata_reg <= s_axi_wdata;
+        temp_m_axi_wstrb_reg <= s_axi_wstrb;
+        temp_m_axi_wlast_reg <= s_axi_wlast;
+        temp_m_axi_wuser_reg <= s_axi_wuser;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (store_axi_w_input_to_temp) begin

temp_m_axi_wdata_reg <= s_axi_wdata;

temp_m_axi_wstrb_reg <= s_axi_wstrb;

temp_m_axi_wlast_reg <= s_axi_wlast;

temp_m_axi_wuser_reg <= s_axi_wuser;

end

end

if (store_axi_w_input_to_temp) begin

temp_m_axi_wdata_reg <= s_axi_wdata;

temp_m_axi_wstrb_reg <= s_axi_wstrb;

temp_m_axi_wlast_reg <= s_axi_wlast;

temp_m_axi_wuser_reg <= s_axi_wuser;

end

end

github-actions · 2024-07-17T14:13:47Z

testbench/axi4_mux/axi_register_wr.v

+end else if (W_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else if (W_REG_TYPE == 1) begin

// simple register, inserts bubble cycles

end else if (W_REG_TYPE == 1) begin

// simple register, inserts bubble cycles

github-actions · 2024-07-17T14:13:47Z

testbench/axi4_mux/axi_register_wr.v

+// datapath registers
+reg                   s_axi_wready_reg = 1'b0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath registers

reg s_axi_wready_reg = 1'b0;

// datapath registers

reg s_axi_wready_reg = 1'b0;

github-actions · 2024-07-17T14:13:47Z

testbench/axi4_mux/axi_register_wr.v

+reg [DATA_WIDTH-1:0]  m_axi_wdata_reg  = {DATA_WIDTH{1'b0}};
+reg [STRB_WIDTH-1:0]  m_axi_wstrb_reg  = {STRB_WIDTH{1'b0}};
+reg                   m_axi_wlast_reg  = 1'b0;
+reg [WUSER_WIDTH-1:0] m_axi_wuser_reg  = {WUSER_WIDTH{1'b0}};
+reg                   m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

reg [DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};

reg [STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};

reg m_axi_wlast_reg = 1'b0;

reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};

reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;

reg [ DATA_WIDTH-1:0] m_axi_wdata_reg = {DATA_WIDTH{1'b0}};

reg [ STRB_WIDTH-1:0] m_axi_wstrb_reg = {STRB_WIDTH{1'b0}};

reg m_axi_wlast_reg = 1'b0;

reg [WUSER_WIDTH-1:0] m_axi_wuser_reg = {WUSER_WIDTH{1'b0}};

reg m_axi_wvalid_reg = 1'b0, m_axi_wvalid_next;

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

github-actions · 2024-07-17T15:18:55Z

testbench/axi4_mux/axi_register_wr.v

+// datapath control
+reg store_axi_w_input_to_output;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath control

reg store_axi_w_input_to_output;

// datapath control

reg store_axi_w_input_to_output;

github-actions · 2024-07-17T15:18:55Z

testbench/axi4_mux/axi_register_wr.v

+// datapath control
+reg store_axi_w_input_to_output;
+
+assign s_axi_wready = s_axi_wready_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign s_axi_wready = s_axi_wready_reg;

assign s_axi_wready = s_axi_wready_reg;

github-actions · 2024-07-17T15:18:55Z

testbench/axi4_mux/axi_register_wr.v

+assign m_axi_wdata  = m_axi_wdata_reg;
+assign m_axi_wstrb  = m_axi_wstrb_reg;
+assign m_axi_wlast  = m_axi_wlast_reg;
+assign m_axi_wuser  = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};
+assign m_axi_wvalid = m_axi_wvalid_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign m_axi_wdata = m_axi_wdata_reg;

assign m_axi_wstrb = m_axi_wstrb_reg;

assign m_axi_wlast = m_axi_wlast_reg;

assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};

assign m_axi_wvalid = m_axi_wvalid_reg;

assign m_axi_wdata = m_axi_wdata_reg;

assign m_axi_wstrb = m_axi_wstrb_reg;

assign m_axi_wlast = m_axi_wlast_reg;

assign m_axi_wuser = WUSER_ENABLE ? m_axi_wuser_reg : {WUSER_WIDTH{1'b0}};

assign m_axi_wvalid = m_axi_wvalid_reg;

github-actions · 2024-07-17T15:18:56Z

testbench/axi4_mux/axi_register_wr.v

+// enable ready input next cycle if output buffer will be empty
+wire s_axi_wready_ewly = !m_axi_wvalid_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// enable ready input next cycle if output buffer will be empty

wire s_axi_wready_ewly = !m_axi_wvalid_next;

// enable ready input next cycle if output buffer will be empty

wire s_axi_wready_ewly = !m_axi_wvalid_next;

github-actions · 2024-07-17T15:18:56Z

testbench/axi4_mux/axi_register_wr.v

+always @* begin
+    // transfer sink ready state to source
+    m_axi_wvalid_next = m_axi_wvalid_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always @* begin

// transfer sink ready state to source

m_axi_wvalid_next = m_axi_wvalid_reg;

always @* begin

// transfer sink ready state to source

m_axi_wvalid_next = m_axi_wvalid_reg;

github-actions · 2024-07-17T15:18:58Z

testbench/axi4_mux/axi_register_wr.v

+            // output is not ready, store input in temp
+            temp_s_axi_bvalid_next = m_axi_bvalid;
+            store_axi_b_input_to_temp = 1'b1;
+        end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

end else if (s_axi_bready) begin

// input is not ready, but output is ready

s_axi_bvalid_next = temp_s_axi_bvalid_reg;

temp_s_axi_bvalid_next = 1'b0;

store_axi_b_temp_to_output = 1'b1;

end

github-actions · 2024-07-17T15:18:58Z

testbench/axi4_mux/axi_register_wr.v

+    end else if (s_axi_bready) begin
+        // input is not ready, but output is ready
+        s_axi_bvalid_next = temp_s_axi_bvalid_reg;
+        temp_s_axi_bvalid_next = 1'b0;
+        store_axi_b_temp_to_output = 1'b1;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else if (s_axi_bready) begin

// input is not ready, but output is ready

s_axi_bvalid_next = temp_s_axi_bvalid_reg;

temp_s_axi_bvalid_next = 1'b0;

store_axi_b_temp_to_output = 1'b1;

end

end

end

github-actions · 2024-07-17T15:18:58Z

testbench/axi4_mux/axi_register_wr.v

+always @(posedge clk) begin
+    if (rst) begin
+        m_axi_bready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+        temp_s_axi_bvalid_reg <= 1'b0;
+    end else begin
+        m_axi_bready_reg <= m_axi_bready_early;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+        temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

always @(posedge clk) begin

if (rst) begin

m_axi_bready_reg <= 1'b0;

s_axi_bvalid_reg <= 1'b0;

temp_s_axi_bvalid_reg <= 1'b0;

end else begin

m_axi_bready_reg <= m_axi_bready_early;

s_axi_bvalid_reg <= s_axi_bvalid_next;

temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;

end

always @(posedge clk) begin

if (rst) begin

m_axi_bready_reg <= 1'b0;

s_axi_bvalid_reg <= 1'b0;

temp_s_axi_bvalid_reg <= 1'b0;

end else begin

m_axi_bready_reg <= m_axi_bready_early;

s_axi_bvalid_reg <= s_axi_bvalid_next;

temp_s_axi_bvalid_reg <= temp_s_axi_bvalid_next;

end

github-actions · 2024-07-17T15:18:58Z

testbench/axi4_mux/axi_register_wr.v

+    // datapath
+    if (store_axi_b_input_to_output) begin
+        s_axi_bid_reg   <= m_axi_bid;
+        s_axi_bresp_reg <= m_axi_bresp;
+        s_axi_buser_reg <= m_axi_buser;
+    end else if (store_axi_b_temp_to_output) begin
+        s_axi_bid_reg   <= temp_s_axi_bid_reg;
+        s_axi_bresp_reg <= temp_s_axi_bresp_reg;
+        s_axi_buser_reg <= temp_s_axi_buser_reg;
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath

if (store_axi_b_input_to_output) begin

s_axi_bid_reg <= m_axi_bid;

s_axi_bresp_reg <= m_axi_bresp;

s_axi_buser_reg <= m_axi_buser;

end else if (store_axi_b_temp_to_output) begin

s_axi_bid_reg <= temp_s_axi_bid_reg;

s_axi_bresp_reg <= temp_s_axi_bresp_reg;

s_axi_buser_reg <= temp_s_axi_buser_reg;

end

// datapath

if (store_axi_b_input_to_output) begin

s_axi_bid_reg <= m_axi_bid;

s_axi_bresp_reg <= m_axi_bresp;

s_axi_buser_reg <= m_axi_buser;

end else if (store_axi_b_temp_to_output) begin

s_axi_bid_reg <= temp_s_axi_bid_reg;

s_axi_bresp_reg <= temp_s_axi_bresp_reg;

s_axi_buser_reg <= temp_s_axi_buser_reg;

end

github-actions · 2024-07-17T15:18:59Z

testbench/axi4_mux/axi_register_wr.v

+    if (store_axi_b_input_to_temp) begin
+        temp_s_axi_bid_reg   <= m_axi_bid;
+        temp_s_axi_bresp_reg <= m_axi_bresp;
+        temp_s_axi_buser_reg <= m_axi_buser;
+    end
+end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

if (store_axi_b_input_to_temp) begin

temp_s_axi_bid_reg <= m_axi_bid;

temp_s_axi_bresp_reg <= m_axi_bresp;

temp_s_axi_buser_reg <= m_axi_buser;

end

end

if (store_axi_b_input_to_temp) begin

temp_s_axi_bid_reg <= m_axi_bid;

temp_s_axi_bresp_reg <= m_axi_bresp;

temp_s_axi_buser_reg <= m_axi_buser;

end

end

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

testbench/jtagdpi/jtagdpi.sv|21|
testbench/jtagdpi/jtagdpi.sv|24|
testbench/jtagdpi/jtagdpi.sv|29|
testbench/jtagdpi/jtagdpi.sv|44|

github-actions · 2024-07-17T16:26:22Z

testbench/axi4_mux/axi_register_wr.v

+end else if (B_REG_TYPE == 1) begin
+// simple register, inserts bubble cycles


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end else if (B_REG_TYPE == 1) begin

// simple register, inserts bubble cycles

end else if (B_REG_TYPE == 1) begin

// simple register, inserts bubble cycles

github-actions · 2024-07-17T16:26:22Z

testbench/axi4_mux/axi_register_wr.v

+// datapath registers
+reg                   m_axi_bready_reg = 1'b0;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath registers

reg m_axi_bready_reg = 1'b0;

// datapath registers

reg m_axi_bready_reg = 1'b0;

github-actions · 2024-07-17T16:26:23Z

testbench/axi4_mux/axi_register_wr.v

+reg [ID_WIDTH-1:0]    s_axi_bid_reg    = {ID_WIDTH{1'b0}};
+reg [1:0]             s_axi_bresp_reg  = 2'b0;
+reg [BUSER_WIDTH-1:0] s_axi_buser_reg  = {BUSER_WIDTH{1'b0}};
+reg                   s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};

reg [1:0] s_axi_bresp_reg = 2'b0;

reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};

reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;

reg [ ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}};

reg [ 1:0] s_axi_bresp_reg = 2'b0;

reg [BUSER_WIDTH-1:0] s_axi_buser_reg = {BUSER_WIDTH{1'b0}};

reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;

github-actions · 2024-07-17T16:26:23Z

testbench/axi4_mux/axi_register_wr.v

+// datapath control
+reg store_axi_b_input_to_output;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

// datapath control

reg store_axi_b_input_to_output;

// datapath control

reg store_axi_b_input_to_output;

github-actions · 2024-07-17T16:26:23Z

testbench/axi4_mux/axi_register_wr.v

+// datapath control
+reg store_axi_b_input_to_output;
+
+assign m_axi_bready = m_axi_bready_reg;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign m_axi_bready = m_axi_bready_reg;

assign m_axi_bready = m_axi_bready_reg;

github-actions · 2024-07-17T16:26:25Z

testbench/axi4_mux/priority_encoder.v

+        for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
+            assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
+            if (LSB_HIGH_PRIORITY) begin
+                // bit 0 is highest priority
+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
+            end else begin
+                // bit 0 is lowest priority
+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
+            end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress

assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];

if (LSB_HIGH_PRIORITY) begin

// bit 0 is highest priority

assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};

end else begin

// bit 0 is lowest priority

assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};

end

for (n = 0; n < W / (2 * 2 ** l); n = n + 1) begin : loop_compress

assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];

if (LSB_HIGH_PRIORITY) begin

// bit 0 is highest priority

assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};

end else begin

// bit 0 is lowest priority

assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};

github-actions · 2024-07-17T16:26:25Z

testbench/axi4_mux/priority_encoder.v

+                assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
+            end
+        end
+    end


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

end

end

end

github-actions · 2024-07-17T16:26:25Z

testbench/axi4_mux/priority_encoder.v

+            end
+        end
+    end
+endgenerate


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

endgenerate

endgenerate

github-actions · 2024-07-17T16:26:25Z

testbench/axi4_mux/priority_encoder.v

+assign output_valid = stage_valid[LEVELS-1];
+assign output_encoded = stage_enc[LEVELS-1];
+assign output_unencoded = 1 << output_encoded;


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

assign output_valid = stage_valid[LEVELS-1];

assign output_encoded = stage_enc[LEVELS-1];

assign output_unencoded = 1 << output_encoded;

assign output_valid = stage_valid[LEVELS-1];

assign output_encoded = stage_enc[LEVELS-1];

assign output_unencoded = 1 << output_encoded;

github-actions · 2024-07-17T16:26:25Z

testbench/jtagdpi/jtagdpi.sv

+  parameter string Name = "jtag0", // name of the JTAG interface (display only)
+  parameter int ListenPort = 44853 // TCP port to listen on
+)(
+  input  logic clk_i,
+  input  logic rst_ni,
+
+  output logic jtag_tck,
+  output logic jtag_tms,
+  output logic jtag_tdi,
+  input  logic jtag_tdo,
+  output logic jtag_trst_n,
+  output logic jtag_srst_n


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

parameter string Name = "jtag0", // name of the JTAG interface (display only)

parameter int ListenPort = 44853 // TCP port to listen on

)(

input logic clk_i,

input logic rst_ni,

output logic jtag_tck,

output logic jtag_tms,

output logic jtag_tdi,

input logic jtag_tdo,

output logic jtag_trst_n,

output logic jtag_srst_n

parameter string Name = "jtag0", // name of the JTAG interface (display only)

parameter int ListenPort = 44853 // TCP port to listen on

) (

input logic clk_i,

input logic rst_ni,

output logic jtag_tck,

output logic jtag_tms,

output logic jtag_tdi,

input logic jtag_tdo,

output logic jtag_trst_n,

output logic jtag_srst_n

github-actions · 2024-07-18T09:05:46Z

testbench/jtagdpi/jtagdpi.sv

+  import "DPI-C"
+  function chandle jtagdpi_create(input string name, input int listen_port);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import "DPI-C"

function chandle jtagdpi_create(input string name, input int listen_port);

import "DPI-C" function chandle jtagdpi_create(

input string name,

input int listen_port

);

github-actions · 2024-07-18T09:05:46Z

testbench/jtagdpi/jtagdpi.sv

+  import "DPI-C"
+  function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,
+                             output bit tdi, output bit trst_n,
+                             output bit srst_n, input bit tdo);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import "DPI-C"

function void jtagdpi_tick(input chandle ctx, output bit tck, output bit tms,

output bit tdi, output bit trst_n,

output bit srst_n, input bit tdo);

import "DPI-C" function void jtagdpi_tick(

input chandle ctx,

output bit tck,

output bit tms,

output bit tdi,

output bit trst_n,

output bit srst_n,

input bit tdo

);

github-actions · 2024-07-18T09:05:46Z

testbench/jtagdpi/jtagdpi.sv

+  import "DPI-C"
+  function void jtagdpi_close(input chandle ctx);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

import "DPI-C"

function void jtagdpi_close(input chandle ctx);

import "DPI-C" function void jtagdpi_close(input chandle ctx);

github-actions · 2024-07-18T09:05:46Z

testbench/jtagdpi/jtagdpi.sv

+    jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
+                 jtag_tdo);


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,

jtag_tdo);

jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n, jtag_tdo);

testbench/ahb_sif.sv

github-actions · 2024-07-18T12:03:12Z

Links to coverage and verification reports for this PR (#211) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-07-19T10:55:23Z

Links to coverage and verification reports for this PR (#211) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-07-19T14:44:07Z

Links to coverage and verification reports for this PR (#211) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions · 2024-07-19T18:47:45Z

Links to coverage and verification reports for this PR (#211) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Internal-tag: [#60812]

github-actions · 2024-07-29T16:45:58Z

Links to coverage and verification reports for this PR (#211) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/

github-actions bot reviewed Jul 16, 2024

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Add openocd test job

800d836

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Add ahb_lite_2to1_mux

9593484

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

RRozak and others added 12 commits July 29, 2024 17:18

Add axi_crossbar

f132e01

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Skip Verilator warnings

1cabd8e

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Fix axi_slv signals

de131c3

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Change width of mux output

e6936e9

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Add licence information

f191c87

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Move tools/openocd to testbench/openocd_scripts

5a32c70

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Handle end of simulation

53bc3ed

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Add ifdefs

9186459

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Fix formatting

ea095e3

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Gather coverage

0376fb1

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Test openocd with ahb_lite bus

b9f67d7

Internal-tag: [#60812] Signed-off-by: Ryszard Rozak <[email protected]>

Remove redeclared signals

4ba3e1a

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tmichalak merged commit 5c9580f into chipsalliance:main Aug 2, 2024
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		parameter AHB_LITE_ADDR_WIDTH = 32,
		parameter AHB_LITE_DATA_WIDTH = 32,

		input wire [PORTS-1:0] request,
		input wire [PORTS-1:0] acknowledge,

	output wire [PORTS-1:0] grant,
	output wire [ PORTS-1:0] grant,

	reg [2:0] state_reg = STATE_IDLE, state_next;
	reg [2:0] state_reg = STATE_IDLE, state_next;


		reg [2:0] state_reg = STATE_IDLE, state_next;

		reg s_axi_aready_reg = 0, s_axi_aready_next;

	assign s_axi_aready = s_axi_aready_reg;
	assign s_axi_aready = s_axi_aready_reg;

	parameter STRB_WIDTH = (DATA_WIDTH/8),
	parameter STRB_WIDTH = (DATA_WIDTH / 8),

	parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
	parameter M_ID_WIDTH = S_ID_WIDTH + $clog2(S_COUNT),

-        always @(posedge clk) begin
-            if (rst) begin
-                w_select_valid_reg <= 1'b0;
-                w_select_new_reg <= 1'b1;
-            end else begin
-                w_select_valid_reg <= w_select_valid_next;
-                w_select_new_reg <= w_select_new_next;
-            end
+        decerr_m_axi_bid_reg <= decerr_m_axi_bid_next;
+      end
+      // write response arbitration
+      wire [M_COUNT_P1-1:0] b_request;
+      wire [M_COUNT_P1-1:0] b_acknowledge;
+      wire [M_COUNT_P1-1:0] b_grant;
+      wire b_grant_valid;
+      wire [CL_M_COUNT_P1-1:0] b_grant_encoded;
+      arbiter #(
+          .PORTS(M_COUNT_P1),
+          .ARB_TYPE_ROUND_ROBIN(1),
+          .ARB_BLOCK(1),
+          .ARB_BLOCK_ACK(1),
+          .ARB_LSB_HIGH_PRIORITY(1)
+      ) b_arb_inst (
+          .clk(clk),
+          .rst(rst),
+          .request(b_request),
+          .acknowledge(b_acknowledge),
+          .grant(b_grant),
+          .grant_valid(b_grant_valid),
+          .grant_encoded(b_grant_encoded)
+      );
+      // write response mux
+      wire [S_ID_WIDTH-1:0]  m_axi_bid_mux    = {decerr_m_axi_bid_reg, int_m_axi_bid} >> b_grant_encoded*M_ID_WIDTH;
+      wire [1:0] m_axi_bresp_mux = {2'b11, int_m_axi_bresp} >> b_grant_encoded * 2;
+      wire [BUSER_WIDTH-1:0] m_axi_buser_mux  = {{BUSER_WIDTH{1'b0}}, int_m_axi_buser} >> b_grant_encoded*BUSER_WIDTH;
+      wire                   m_axi_bvalid_mux = ({decerr_m_axi_bvalid_reg, int_m_axi_bvalid} >> b_grant_encoded) & b_grant_valid;
+      wire m_axi_bready_mux;
+      assign int_axi_bready[m*M_COUNT +: M_COUNT] = (b_grant_valid && m_axi_bready_mux) << b_grant_encoded;
+      assign decerr_m_axi_bready = (b_grant_valid && m_axi_bready_mux) && (b_grant_encoded == M_COUNT_P1-1);
+      for (n = 0; n < M_COUNT; n = n + 1) begin
+        assign b_request[n] = int_axi_bvalid[n*S_COUNT+m] && !b_grant[n];
+        assign b_acknowledge[n] = b_grant[n] && int_axi_bvalid[n*S_COUNT+m] && m_axi_bready_mux;
+      end
+      assign b_request[M_COUNT_P1-1] = decerr_m_axi_bvalid_reg && !b_grant[M_COUNT_P1-1];
+      assign b_acknowledge[M_COUNT_P1-1] = b_grant[M_COUNT_P1-1] && decerr_m_axi_bvalid_reg && m_axi_bready_mux;
+      assign s_cpl_id = m_axi_bid_mux;
+      assign s_cpl_valid = m_axi_bvalid_mux && m_axi_bready_mux;
+      // S side register
+      axi_register_wr #(
+          .DATA_WIDTH(DATA_WIDTH),
+          .ADDR_WIDTH(ADDR_WIDTH),
+          .STRB_WIDTH(STRB_WIDTH),
+          .ID_WIDTH(S_ID_WIDTH),
+          .AWUSER_ENABLE(AWUSER_ENABLE),
+          .AWUSER_WIDTH(AWUSER_WIDTH),
+          .WUSER_ENABLE(WUSER_ENABLE),
+          .WUSER_WIDTH(WUSER_WIDTH),
+          .BUSER_ENABLE(BUSER_ENABLE),
+          .BUSER_WIDTH(BUSER_WIDTH),
+          .AW_REG_TYPE(S_AW_REG_TYPE[m*2+:2]),
+          .W_REG_TYPE(S_W_REG_TYPE[m*2+:2]),
+          .B_REG_TYPE(S_B_REG_TYPE[m*2+:2])
+      ) reg_inst (
+          .clk(clk),
+          .rst(rst),
+          .s_axi_awid(s_axi_awid[m*S_ID_WIDTH+:S_ID_WIDTH]),
+          .s_axi_awaddr(s_axi_awaddr[m*ADDR_WIDTH+:ADDR_WIDTH]),
+          .s_axi_awlen(s_axi_awlen[m*8+:8]),
+          .s_axi_awsize(s_axi_awsize[m*3+:3]),
+          .s_axi_awburst(s_axi_awburst[m*2+:2]),
+          .s_axi_awlock(s_axi_awlock[m]),
+          .s_axi_awcache(s_axi_awcache[m*4+:4]),
+          .s_axi_awprot(s_axi_awprot[m*3+:3]),
+          .s_axi_awqos(s_axi_awqos[m*4+:4]),
+          .s_axi_awregion(4'd0),
+          .s_axi_awuser(s_axi_awuser[m*AWUSER_WIDTH+:AWUSER_WIDTH]),
+          .s_axi_awvalid(s_axi_awvalid[m]),
+          .s_axi_awready(s_axi_awready[m]),
+          .s_axi_wdata(s_axi_wdata[m*DATA_WIDTH+:DATA_WIDTH]),
+          .s_axi_wstrb(s_axi_wstrb[m*STRB_WIDTH+:STRB_WIDTH]),
+          .s_axi_wlast(s_axi_wlast[m]),
+          .s_axi_wuser(s_axi_wuser[m*WUSER_WIDTH+:WUSER_WIDTH]),
+          .s_axi_wvalid(s_axi_wvalid[m]),
+          .s_axi_wready(s_axi_wready[m]),
+          .s_axi_bid(s_axi_bid[m*S_ID_WIDTH+:S_ID_WIDTH]),
+          .s_axi_bresp(s_axi_bresp[m*2+:2]),
+          .s_axi_buser(s_axi_buser[m*BUSER_WIDTH+:BUSER_WIDTH]),
+          .s_axi_bvalid(s_axi_bvalid[m]),
+          .s_axi_bready(s_axi_bready[m]),
+          .m_axi_awid(int_s_axi_awid[m*S_ID_WIDTH+:S_ID_WIDTH]),
+          .m_axi_awaddr(int_s_axi_awaddr[m*ADDR_WIDTH+:ADDR_WIDTH]),
+          .m_axi_awlen(int_s_axi_awlen[m*8+:8]),
+          .m_axi_awsize(int_s_axi_awsize[m*3+:3]),
+          .m_axi_awburst(int_s_axi_awburst[m*2+:2]),
+          .m_axi_awlock(int_s_axi_awlock[m]),
+          .m_axi_awcache(int_s_axi_awcache[m*4+:4]),
+          .m_axi_awprot(int_s_axi_awprot[m*3+:3]),
+          .m_axi_awqos(int_s_axi_awqos[m*4+:4]),
+          .m_axi_awregion(),
+          .m_axi_awuser(int_s_axi_awuser[m*AWUSER_WIDTH+:AWUSER_WIDTH]),
+          .m_axi_awvalid(int_s_axi_awvalid[m]),
+          .m_axi_awready(int_s_axi_awready[m]),
+          .m_axi_wdata(int_s_axi_wdata[m*DATA_WIDTH+:DATA_WIDTH]),
+          .m_axi_wstrb(int_s_axi_wstrb[m*STRB_WIDTH+:STRB_WIDTH]),
+          .m_axi_wlast(int_s_axi_wlast[m]),
+          .m_axi_wuser(int_s_axi_wuser[m*WUSER_WIDTH+:WUSER_WIDTH]),
+          .m_axi_wvalid(int_s_axi_wvalid[m]),
+          .m_axi_wready(int_s_axi_wready[m]),
+          .m_axi_bid(m_axi_bid_mux),
+          .m_axi_bresp(m_axi_bresp_mux),
+          .m_axi_buser(m_axi_buser_mux),
+          .m_axi_bvalid(m_axi_bvalid_mux),
+          .m_axi_bready(m_axi_bready_mux)
+      );
+    end  // s_ifaces

	module axi_crossbar_wrap_2x1 #
	(
	module axi_crossbar_wrap_2x1 #(

	store_axi_r_input_to_output = 1'b0;
	store_axi_r_input_to_output = 1'b0;

		end else if (W_REG_TYPE == 1) begin
		// simple register, inserts bubble cycles

	assign s_axi_wready = s_axi_wready_reg;
	assign s_axi_wready = s_axi_wready_reg;

		// enable ready input next cycle if output buffer will be empty
		wire s_axi_wready_ewly = !m_axi_wvalid_next;

		end else if (B_REG_TYPE == 1) begin
		// simple register, inserts bubble cycles

	assign m_axi_bready = m_axi_bready_reg;
	assign m_axi_bready = m_axi_bready_reg;

		import "DPI-C"
		function chandle jtagdpi_create(input string name, input int listen_port);

		import "DPI-C"
		function void jtagdpi_close(input chandle ctx);

	import "DPI-C"
	function void jtagdpi_close(input chandle ctx);
	import "DPI-C" function void jtagdpi_close(input chandle ctx);

		jtagdpi_tick(ctx, jtag_tck, jtag_tms, jtag_tdi, jtag_trst_n, jtag_srst_n,
		jtag_tdo);

Add OpenOCD test #211

Add OpenOCD test #211

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