Skip to content

Issues: chipsalliance/Cores-VeeR-EL2

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

21 Open 61 Closed
21 Open 61 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

JTAGDPI Error when trying to simulate hello world using questasim
#277 opened Nov 21, 2024 by jannathundal
EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
#169 opened May 13, 2024 by xiaolei-cheng
Relation between Core reset(rst_l) and dbg_rst_l
#168 opened Apr 27, 2024 by Syed-mudabbir-ahsan
Request to review Lint Issues in Veer RTL
#166 opened Apr 6, 2024 by amullick007
2
FuseSoC core description file is missing
#165 opened Mar 27, 2024 by olofk
Remove (or make optional) the JTAG IDCODE command
#146 opened Dec 11, 2023 by calebofearth
6
WFI instruction is missing?
#104 opened Jul 5, 2023 by Risto97
Replacing hand instantiated synchronizer flops
#103 opened Jun 30, 2023 by nstewart-amd
1
Next PC not sampled when core wakes up from sleep in Verilator run
#88 opened Jun 7, 2023 by upadhyayulakiran
4
VeeR defines uniquification
#59 opened Feb 17, 2023 by nstewart-amd
RV_ASSERT_ON is always enabled
#58 opened Feb 17, 2023 by nstewart-amd
5
EL2 Memory Interface ​Synthesis Compatibility
#57 opened Feb 17, 2023 by nstewart-amd
synchronizers implemented as synthesizable flops
#51 opened Jan 18, 2023 by rahuljainNV
3
Replacing hand instantiated clock gate cells
#50 opened Jan 18, 2023 by rahuljainNV
9
Hiding assertions code from design tools
#49 opened Jan 18, 2023 by rahuljainNV
12
branch prediction understanding
#40 opened Mar 27, 2022 by KinzaQamar
display statement in el2_ifu.sv
#39 opened Mar 25, 2022 by KinzaQamar
6
understanding Branch Prediction
#37 opened Dec 12, 2021 by KinzaQamar
2
critical path is from DCCM to ICCM ？
#18 opened Nov 24, 2020 by yzt000000
1
Synthesis clock speed is very slow
#16 opened Nov 9, 2020 by kidonglee
6
ROM for EL2
#8 opened Aug 21, 2020 by altuSemi
ProTip! Exclude everything labeled bug with -label:bug.