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Fix riscv-dv makefile
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Internal-tag: [#60812]
Signed-off-by: Ryszard Rozak <[email protected]>
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RRozak committed Jul 17, 2024
1 parent fce2993 commit 62227d4
Showing 1 changed file with 7 additions and 2 deletions.
9 changes: 7 additions & 2 deletions tools/riscv-dv/Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,6 @@ endif
VERILATOR = verilator
VERILATOR_CFLAGS = -std=c++14
VERILATOR_INC = -I$(WORK_DIR) -I$(RV_ROOT)/testbench -I$(RV_ROOT)/testbench/axi4_mux
VERILATOR_EXE = $(RV_ROOT)/testbench/test_tb_top.cpp

HDL_FILES = $(WORK_DIR)/common_defines.vh \
$(WORK_DIR)/el2_pdef.vh \
Expand All @@ -50,6 +49,12 @@ TB_DPI_INCS := $(addprefix -I$(RV_ROOT)/testbench/,$(dir $(TB_DPI_SRCS)))
# Add testbench include paths
VERILATOR_CFLAGS += $(TB_DPI_INCS)

TB_DPI_SRCS := $(addprefix $(RV_ROOT)/testbench/,$(TB_DPI_SRCS))
TB_CPP_SRCS = $(RV_ROOT)/testbench/test_tb_top.cpp $(TB_DPI_SRCS)

VERILATOR_SKIP_WARNINGS = -Wno-IMPLICITSTATIC -Wno-TIMESCALEMOD -Wno-ASCRANGE \
-Wno-CASEINCOMPLETE -Wno-INITIALDLY -Wno-WIDTH -Wno-UNOPTFLAT

# riscv-dv args
RISCV_DV_ARGS = \
--simulator $(RISCV_DV_SIM) \
Expand Down Expand Up @@ -85,7 +90,7 @@ $(WORK_DIR)/defines.h: | $(WORK_DIR)
$(WORK_DIR)/verilator/Vtb_top.mk: $(WORK_DIR)/defines.h
$(VERILATOR) --cc -CFLAGS "$(VERILATOR_CFLAGS)" $(VERILATOR_INC) \
$(HDL_FILES) -f $(RV_ROOT)/testbench/flist --top-module tb_top \
-exe $(VERILATOR_EXE) -Wno-WIDTH -Wno-UNOPTFLAT -Wno-IMPLICITSTATIC --autoflush \
-exe $(TB_CPP_SRCS) $(VERILATOR_SKIP_WARNINGS) --timing --autoflush \
$(VERILATOR_COVERAGE) \
-Mdir $(WORK_DIR)/verilator

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