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Issues: alexforencich/verilog-axi
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axi_dma_wr seems to give done status before fully writing to DDR?
#80
opened Jul 16, 2024 by
abarajithan11
Parameters not passed on to axi_crossbar_wr and axi_crossbar_rd in axi_crossbar.v
#79
opened Jul 1, 2024 by
RiceShelley
Q: Do axi_dma_rd and axi_dma_wr support out of order transactions?
#60
opened Nov 1, 2023 by
abarajithan11
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