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about AXI_VFIFO #59
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I did further research in the decoding module, but I am not a Verilog developer and therefore limited in my analysis. But I identified the following signals as part of the problem: seg_empty is 1 because the wr and rd pointers are the same. No write is triggered because ctrl_fifo_wr_en remains 0, although the SOP is recognised see ctrl_fifo_wr_sop. Is ctrl_fifo_wr_en not set because seg_valid[1] = Undefined? And why is this a 2 bit vector? |
Hi, currently I set axi_data_width=256, ch = 1, and then set axis_data_width=axi_data_width/2, max_seg_width = axi_data_width/2, and then the vfifo works. if axi_ch=1 then set axis_data_width=axi_data_width and max_seg_width = axi_data_width, parameter SEG_CNT will to be 1, and parameters in encode/decode fifo are not correctly calculated and the vfifo will failed. Thanks, please take a review. |
I tried to use the AXI_vfifo module you wrote, and I tried to configure it as a single channel FIFO. The other side is connected to a DDR MIG controller, it seems that the input of the FIFO is normal, and the AXI reading and writing of the MIG are also normal, but the FIFO has no output. I don't know where the problem lies at the moment
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