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Hi, first of all, thank you for the IP cores! Made my life so much easier than using Xilinx IP Cores :)
I am pretty new to FPGA Design and am struggling a bit so please excuse if this question in itself is trivial and for more seasoned developer obvious.
I am using the DMA core. I have figured out how to use it via the descriptor names.
However, I can't figure out when the IP Core is done?
My best guess would be *status_valid or *_status_error flags.
Surely, there is some documentation, which explains stuff like this.. Could you point me in the right direction?
The text was updated successfully, but these errors were encountered:
Hi, first of all, thank you for the IP cores! Made my life so much easier than using Xilinx IP Cores :)
I am pretty new to FPGA Design and am struggling a bit so please excuse if this question in itself is trivial and for more seasoned developer obvious.
I am using the DMA core. I have figured out how to use it via the descriptor names.
However, I can't figure out when the IP Core is done?
My best guess would be
*status_valid
or*_status_error
flags.Surely, there is some documentation, which explains stuff like this.. Could you point me in the right direction?
The text was updated successfully, but these errors were encountered: