The range of m_select_reg becomes ascending

[offnaria]

Hello,

I'm trying to use axi_interconnect to arbitrate multicore processors by setting M_COUNT = 1.
However, in this case, CL_M_COUNT = $clog2(M_COUNT) becomes 0, and then some registers are declared as reg [-1:0] at the following line, leading Verilator to send a warning.

verilog-axi/rtl/axi_interconnect.v

Line 306 in 38915fb

reg [CL_M_COUNT-1:0] m_select_reg = 2'd0, m_select_next;

Since s_select wire is declared as wire [(CL_S_COUNT > 0 ? CL_S_COUNT-1 : 0):0] s_select;, how about declaring these registers in the same manner?