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[Draft] ✨ 🐛 Bug fixes and vstart CSR support #270

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c3b3459
dpi: Fix symlink
niwis Jul 28, 2022
f915444
ara_soc: Fix Ariane config param
niwis Nov 15, 2022
1ed7630
tech_cells_generic: Bump
niwis Dec 21, 2022
56b64f1
Makefile: Demote verilate warnings
niwis Dec 21, 2022
05168f4
ara_system: Propatage AXI parameters to CVA6
niwis Dec 21, 2022
feb8bee
Revert "tech_cells_generic: Bump"
mp-17 Dec 21, 2022
b32e252
[DEBUG-COMMIT] Don't make entire mtx fail because of bender
mp-17 Dec 21, 2022
f248316
hw/Makefile: Update CVA6 target and defines
niwis Dec 23, 2022
30be632
[scripts] Increase HW-SW cycle check delta
mp-17 Jan 10, 2023
bc46525
cva6: Bump
niwis May 16, 2023
92f7348
hw/Makefile: Update CVA6 target
niwis May 16, 2023
421c921
Bender.yml: Update cva6 rev
niwis May 16, 2023
143103f
vmfpu: Remove unavailable fpnew ports
niwis May 17, 2023
b08b588
ara_soc: Upgrade axi to apb
niwis May 17, 2023
7a84db4
cva6: Bump
niwis May 17, 2023
e61e91f
Bender.yml: Rename package ariane to cva6
niwis May 17, 2023
bb6c36d
[hardware] Adapt vmfpu module
mp-17 Mar 17, 2023
ac2465a
cva6: Bump
niwis Jun 16, 2023
c2a4846
cva6: Bump (remove stall signls)
niwis Jun 18, 2023
d14b438
cva6: Bump (move accel_disp and merge commit)
niwis Jun 18, 2023
a025985
cva6: Bump (merge ctrl)
niwis Jun 19, 2023
604cb54
scripts/wave_core.tcl: Update CVA6 module hierarchy
niwis Jun 19, 2023
184b55e
cva6: Bump (merge issue)
niwis Jun 19, 2023
b588e86
cva6: Bump (move decoder)
niwis Jun 20, 2023
e061590
cva6_accel_first_pass_decoder: Merge other accel decode logic
niwis Jun 20, 2023
83e78cc
cva6: Bump (unify interfaces)
niwis Jun 20, 2023
0ec0cb0
cva6: Unify accelerator and CVX interface
niwis Jun 20, 2023
e926308
cva6: Bump (move issue logic)
niwis Jun 20, 2023
8dcd5b3
Extended sw build for Linux
MaistoV Sep 12, 2023
6fda8cd
Update submodules
MaistoV Sep 13, 2023
22df89b
Fix bender download
MaistoV Sep 13, 2023
878db16
Set LINUX=0 as default
MaistoV Sep 13, 2023
5c233aa
Refactoring addrgen
MaistoV Sep 13, 2023
cf97647
Restoring default INSALL_DIR
MaistoV Sep 13, 2023
018af66
Extensions and bug fixes
MaistoV Sep 29, 2023
f08c28f
Supporting vstart CSR for operand read, VALU, VLSU
MaistoV Oct 13, 2023
551d597
tmp commit
MaistoV Oct 16, 2023
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cva6: Unify accelerator and CVX interface
Signed-off-by: Nils Wistoff <[email protected]>
niwis committed Jun 20, 2023

Verified

This commit was signed with the committer’s verified signature.
niwis Nils Wistoff
commit 0ec0cb0824bf76a16d27af49d44b02844330faf4
4 changes: 2 additions & 2 deletions hardware/include/ara_pkg.sv
Original file line number Diff line number Diff line change
@@ -239,8 +239,8 @@ package ara_pkg;
/////////////////////////////

// Use Ariane's accelerator interface.
typedef ariane_pkg::accelerator_req_t accelerator_req_t;
typedef ariane_pkg::accelerator_resp_t accelerator_resp_t;
typedef acc_pkg::accelerator_req_t accelerator_req_t;
typedef acc_pkg::accelerator_resp_t accelerator_resp_t;

/////////////////////////
// Backend interface //
84 changes: 42 additions & 42 deletions hardware/scripts/wave_core.tcl
Original file line number Diff line number Diff line change
@@ -4,62 +4,62 @@
#
# Author: Matheus Cavalcante <[email protected]>

add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/*
add wave -noupdate -group CVA6 -group core /ara_tb/dut/i_ara_soc/i_system/i_ariane/*

add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/*
add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_cva6_icache/*
# add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_ras/*
# add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_btb/*
# add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_bht/*
# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/*/i_instr_scan/*
# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/i_frontend/i_fetch_fifo/*
add wave -noupdate -group CVA6 -group frontend /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/*
add wave -noupdate -group CVA6 -group frontend -group icache /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/*
# add wave -noupdate -group CVA6 -group frontend -group ras /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_ras/*
# add wave -noupdate -group CVA6 -group frontend -group btb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_btb/*
# add wave -noupdate -group CVA6 -group frontend -group bht /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_bht/*
# add wave -noupdate -group CVA6 -group frontend -group instr_scan /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/*/i_instr_scan/*
# add wave -noupdate -group CVA6 -group frontend -group fetch_fifo /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_frontend/i_fetch_fifo/*

add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/decoder_i/*
add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/genblk1/compressed_decoder_i/*
add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/id_stage_i/*
add wave -noupdate -group CVA6 -group id_stage -group decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/decoder_i/*
add wave -noupdate -group CVA6 -group id_stage -group compressed_decoder /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/genblk1/compressed_decoder_i/*
add wave -noupdate -group CVA6 -group id_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/id_stage_i/*

add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_scoreboard/*
add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_issue_read_operands/*
add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/i_re_name/*
add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/issue_stage_i/*
add wave -noupdate -group CVA6 -group issue_stage -group scoreboard /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_scoreboard/*
add wave -noupdate -group CVA6 -group issue_stage -group issue_read_operands /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_issue_read_operands/*
add wave -noupdate -group CVA6 -group issue_stage -group rename /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/i_re_name/*
add wave -noupdate -group CVA6 -group issue_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/issue_stage_i/*

add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/alu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/*
add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_multiplier/*
add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/i_mult/i_div/*
add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/*
add wave -noupdate -group CVA6 -group ex_stage -group alu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/alu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group mult /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/*
add wave -noupdate -group CVA6 -group ex_stage -group mult -group mul /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_multiplier/*
add wave -noupdate -group CVA6 -group ex_stage -group mult -group div /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/i_mult/i_div/*
add wave -noupdate -group CVA6 -group ex_stage -group fpu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group fpu -group fpnew /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/fpu_gen/fpu_i/fpu_gen/i_fpnew_bulk/*

add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/lsu_bypass_i/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_itlb/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_dtlb/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_ptw/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group lsu_bypass /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/lsu_bypass_i/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group itlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_itlb/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group dtlb /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_dtlb/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group mmu -group ptw /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/gen_mmu_sv39/i_cva6_mmu/i_ptw/*

add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group store_unit -group store_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_store_unit/store_buffer_i/*

add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/lsu_i/i_load_unit/*
add wave -noupdate -group CVA6 -group ex_stage -group lsu -group load_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/lsu_i/i_load_unit/*

add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/branch_unit_i/*
add wave -noupdate -group CVA6 -group ex_stage -group branch_unit /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/branch_unit_i/*

add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/csr_buffer_i/*
add wave -noupdate -group CVA6 -group ex_stage -group csr_buffer /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/csr_buffer_i/*

add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/ex_stage_i/*
add wave -noupdate -group CVA6 -group ex_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/ex_stage_i/*

add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/commit_stage_i/*
add wave -noupdate -group CVA6 -group commit_stage /ara_tb/dut/i_ara_soc/i_system/i_ariane/commit_stage_i/*

add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/csr_regfile_i/*
add wave -noupdate -group CVA6 -group csr_file /ara_tb/dut/i_ara_soc/i_system/i_ariane/csr_regfile_i/*

add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/controller_i/*
add wave -noupdate -group CVA6 -group controller /ara_tb/dut/i_ara_soc/i_system/i_ariane/controller_i/*

add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/*
add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/*
add wave -noupdate -group CVA6 -group wt_dcache /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/*
add wave -noupdate -group CVA6 -group wt_dcache -group miss_handler /ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/i_wt_dcache_missunit/*

add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*}
add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*}
add wave -noupdate -group CVA6 -group wt_dcache -group load {/ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[0]/i_wt_dcache_ctrl/*}
add wave -noupdate -group CVA6 -group wt_dcache -group ptw {/ara_tb/dut/i_ara_soc/i_system/i_ariane/genblk4/i_cache_subsystem/i_wt_dcache/gen_rd_ports[1]/i_wt_dcache_ctrl/*}

add wave -noupdate -group CVA6 -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_accelerator/i_acc_dispatcher/*
add wave -noupdate -group CVA6 -group dispatcher /ara_tb/dut/i_ara_soc/i_system/i_ariane/gen_accelerator/i_acc_dispatcher/*

add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/i_cva6/gen_perf_counter/perf_counters_i/*
add wave -noupdate -group CVA6 -group perf_counters /ara_tb/dut/i_ara_soc/i_system/i_ariane/gen_perf_counter/perf_counters_i/*
28 changes: 12 additions & 16 deletions hardware/src/accel_dispatcher_ideal.sv
Original file line number Diff line number Diff line change
@@ -25,11 +25,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
input logic rst_ni,
// Accelerator interaface
output accelerator_req_t acc_req_o,
output logic acc_req_valid_o,
input logic acc_req_ready_i,
input accelerator_resp_t acc_resp_i,
input logic acc_resp_valid_i,
output logic acc_resp_ready_o
input accelerator_resp_t acc_resp_i
);

localparam string vtrace = `STRINGIFY(`VTRACE);
@@ -69,7 +65,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
status_cnt_n = status_cnt_q;
fifo_data_raw = fifo_q[read_pointer_q];

if (acc_req_ready_i && ~fifo_empty) begin
if (acc_resp_i.req_ready && ~fifo_empty) begin
// read from the queue is a default assignment
// but increment the read pointer...
if (read_pointer_n == N_VINSN - 1)
@@ -94,16 +90,16 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (

assign fifo_empty = (status_cnt_q == 0);

// Always valid until empty
assign acc_req_valid_o = ~fifo_empty;
// Flush the answer
assign acc_resp_ready_o = 1'b1;
// Output assignment
assign fifo_data = fifo_payload_t'(fifo_data_raw);
assign acc_req_o = '{
insn : fifo_data.insn,
rs1 : fifo_data.rs1,
rs2 : fifo_data.rs2,
// Always valid until empty
req_valid : ~fifo_empty,
// Flush the answer
resp_ready : 1'b1,
default : '0
};

@@ -133,7 +129,7 @@ module accel_dispatcher_ideal import axi_pkg::*; import ara_pkg::*; (
// Stop the computation when the instructions are over and ara has returned idle
// Just check that we are after reset
always_ff @(posedge clk_i) begin
if (rst_ni && was_reset && !acc_req_valid_o && i_system.i_ara.ara_idle) begin
if (rst_ni && was_reset && !acc_req_o.req_valid && i_system.i_ara.ara_idle) begin
$display("[hw-cycles]: %d", int'(perf_cnt_q));
$info("Core Test ", $sformatf("*** SUCCESS *** (tohost = %0d)", 0));
$finish(0);
@@ -160,10 +156,10 @@ endmodule
fifo_payload_t payload;

acc_req_o = '0;
acc_req_valid_o = 1'b0;
acc_req_o.req_valid = 1'b0;

// Flush the answer
acc_resp_ready_o = 1'b1;
acc_req_o.resp_ready = 1'b1;

acc_req_o = '0;
acc_req_o.frm = fpnew_pkg::RNE;
@@ -176,17 +172,17 @@ endmodule

while ($fscanf(fd, "%h", payload) == 1) begin
// Always valid
acc_req_valid_o = 1'b1;
acc_req_o.req_valid = 1'b1;
acc_req_o.insn = payload.insn;
acc_req_o.rs1 = payload.rs1;
// Wait for the handshake
wait(acc_req_ready_i);
wait(acc_resp_i.req_ready);
@(posedge clk_i);
@(negedge clk_i);
end

// Stop dispatching
acc_req_valid_o = 1'b0;
acc_req_o.req_valid = 1'b0;

$fclose(fd);
end
8 changes: 0 additions & 8 deletions hardware/src/ara.sv
Original file line number Diff line number Diff line change
@@ -39,11 +39,7 @@ module ara import ara_pkg::*; #(
output logic scan_data_o,
// Interface with Ariane
input accelerator_req_t acc_req_i,
input logic acc_req_valid_i,
output logic acc_req_ready_o,
output accelerator_resp_t acc_resp_o,
output logic acc_resp_valid_o,
input logic acc_resp_ready_i,
// AXI interface
output axi_req_t axi_req_o,
input axi_resp_t axi_resp_i
@@ -95,11 +91,7 @@ module ara import ara_pkg::*; #(
.rst_ni (rst_ni ),
// Interface with Ariane
.acc_req_i (acc_req_i ),
.acc_req_valid_i (acc_req_valid_i ),
.acc_req_ready_o (acc_req_ready_o ),
.acc_resp_o (acc_resp_o ),
.acc_resp_valid_o (acc_resp_valid_o),
.acc_resp_ready_i (acc_resp_ready_i),
// Interface with the sequencer
.ara_req_o (ara_req ),
.ara_req_valid_o (ara_req_valid ),
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