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[Draft] ✨ 🐛 Bug fixes and vstart CSR support #270

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wants to merge 37 commits into from
Closed

[Draft] ✨ 🐛 Bug fixes and vstart CSR support #270

wants to merge 37 commits into from

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MaistoV
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@MaistoV MaistoV commented Dec 4, 2023 •
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This PR aims to introduce:

  • Various bug fixes (including exception geneation and handling) .
  • Extensive support for RVV CSR vstart.
  • Extended tests for new features and fixed bugs (rvv_tests in Cheshire)

NOTE This is a draft PR for subsequent reworking and discussion

Changelog

TBD

Fixed

  • Description of changes (TBD)

Added

  • Description of changes (TBD)

Changed

  • Description of changes (TBD)

Checklist (TBD)

  • Automated tests pass
  • Changelog updated
  • Code style guideline is observed

Please check our contributing guidelines before opening a Pull Request.

niwis and others added 30 commits May 16, 2023 09:45
@niwis
dpi: Fix symlink
c3b3459 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
ara_soc: Fix Ariane config param
f915444 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
tech_cells_generic: Bump
1ed7630 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
Makefile: Demote verilate warnings
56b64f1 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
ara_system: Propatage AXI parameters to CVA6
05168f4 
Signed-off-by: Nils Wistoff <[email protected]>
@mp-17 @niwis
Revert "tech_cells_generic: Bump"
feb8bee 
This reverts commit 304e4f8.
@mp-17 @niwis
[DEBUG-COMMIT] Don't make entire mtx fail because of bender
b32e252
@niwis
hw/Makefile: Update CVA6 target and defines
f248316 
Signed-off-by: Nils Wistoff <[email protected]>
@mp-17 @niwis
[scripts] Increase HW-SW cycle check delta
30be632 
CVA6 bump made some checks fail with the restrictive 300 cycles threshold
@niwis
cva6: Bump
bc46525 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
hw/Makefile: Update CVA6 target
92f7348 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
Bender.yml: Update cva6 rev
421c921 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
vmfpu: Remove unavailable fpnew ports
143103f 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
ara_soc: Upgrade axi to apb
b08b588 
axi2apb_64_32 has been deprecated. Replace it by the up-to-date axi and
apb IPs.

Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump
7a84db4 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
Bender.yml: Rename package ariane to cva6
e61e91f 
Signed-off-by: Nils Wistoff <[email protected]>
@mp-17 @niwis
[hardware] Adapt vmfpu module
bb6c36d 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump
ac2465a 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (remove stall signls)
c2a4846 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (move accel_disp and merge commit)
d14b438 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (merge ctrl)
a025985 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
scripts/wave_core.tcl: Update CVA6 module hierarchy
604cb54 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (merge issue)
184b55e 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (move decoder)
b588e86 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6_accel_first_pass_decoder: Merge other accel decode logic
e061590 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (unify interfaces)
83e78cc 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Unify accelerator and CVX interface
0ec0cb0 
Signed-off-by: Nils Wistoff <[email protected]>
@niwis
cva6: Bump (move issue logic)
e926308 
Signed-off-by: Nils Wistoff <[email protected]>
@MaistoV
Extended sw build for Linux
8dcd5b3 
* Added LINUX switch, default LINUX=1
@MaistoV
Update submodules
6fda8cd 
* Switch from pulp-platform/cva6 to MaistoV/cva6_fork

* Bump axi to v0.39.0
MaistoV and others added 7 commits September 13, 2023 17:17
@MaistoV
Fix bender download
22df89b 
* Bender binaries for some platforms are not supported, e.g, AlmaLinux. Download generic bender for x86_64-linux, instead of platform-dependent.
@MaistoV
Set LINUX=0 as default
878db16
@MaistoV
Refactoring addrgen
5c233aa
@MaistoV
Restoring default INSALL_DIR
cf97647
@MaistoV
Extensions and bug fixes
018af66 
* Stall CSR operations if there is a pending vector instruction

* Set vstart=0 for succesful vector instructions

* Add MMU interface and extend addrgen FSMs (untested)

* Extend and fix Ara exception reporting from VLSU

* Refactoring
@MaistoV
Supporting vstart CSR for operand read, VALU, VLSU
f08c28f 
* vstart support for vector unit-stride loads and stores

* vstart support for vector strided loads and stores

* vstart support for valu operations, mask operations not tested

* Preliminary work on vstart support for vector indexed loads and stores

* Minor fixes

* Refactoring

* Explanatory comments
@MaistoV
tmp commit
551d597
@mp-17 mp-17 mentioned this pull request Jun 19, 2024
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mp-17 commented Jun 19, 2024

Handling this PR in #308

@mp-17 mp-17 closed this Jun 19, 2024
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