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[HW] Draft PR for Implementing Ara on FPGA #146

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4 changes: 4 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -34,3 +34,7 @@ install
pyenv_ara/
docs/build/
docs/source/_templates/
*.jou
fusesoc.conf
.Xil/
*.str
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -32,3 +32,6 @@
path = toolchain/riscv-llvm
url = https://github.com/llvm/llvm-project.git
ignore = dirty
[submodule "hardware/deps/apb_uart"]
path = hardware/deps/apb_uart
url = https://github.com/pulp-platform/apb_uart.git
352 changes: 352 additions & 0 deletions ara.core

Large diffs are not rendered by default.

1 change: 1 addition & 0 deletions fpga/constraints/ara.xdc
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
create_clock -period 13.334 -name clk_i [get_ports clk_i]
81 changes: 81 additions & 0 deletions fpga/constraints/xcu280.xdc
Original file line number Diff line number Diff line change
@@ -0,0 +1,81 @@

## Ara SOC
set_property -dict {PACKAGE_PIN BE41 IOSTANDARD LVCMOS18} [get_ports exit_o[63]]
set_property -dict {PACKAGE_PIN BD41 IOSTANDARD LVCMOS18} [get_ports exit_o[62]]
set_property -dict {PACKAGE_PIN BF46 IOSTANDARD LVCMOS18} [get_ports exit_o[61]]
set_property -dict {PACKAGE_PIN BF45 IOSTANDARD LVCMOS18} [get_ports exit_o[60]]
set_property -dict {PACKAGE_PIN BF43 IOSTANDARD LVCMOS18} [get_ports exit_o[59]]
set_property -dict {PACKAGE_PIN BF42 IOSTANDARD LVCMOS18} [get_ports exit_o[58]]
set_property -dict {PACKAGE_PIN BE46 IOSTANDARD LVCMOS18} [get_ports exit_o[57]]
set_property -dict {PACKAGE_PIN BE45 IOSTANDARD LVCMOS18} [get_ports exit_o[56]]
set_property -dict {PACKAGE_PIN BD42 IOSTANDARD LVCMOS18} [get_ports exit_o[55]]
set_property -dict {PACKAGE_PIN BC42 IOSTANDARD LVCMOS18} [get_ports exit_o[54]]
set_property -dict {PACKAGE_PIN BE44 IOSTANDARD LVCMOS18} [get_ports exit_o[53]]
set_property -dict {PACKAGE_PIN BE43 IOSTANDARD LVCMOS18} [get_ports exit_o[52]]
set_property -dict {PACKAGE_PIN BL50 IOSTANDARD LVCMOS18} [get_ports exit_o[51]]
set_property -dict {PACKAGE_PIN BL48 IOSTANDARD LVCMOS18} [get_ports exit_o[50]]
set_property -dict {PACKAGE_PIN BF53 IOSTANDARD LVCMOS18} [get_ports exit_o[49]]
set_property -dict {PACKAGE_PIN BG47 IOSTANDARD LVCMOS18} [get_ports exit_o[48]]
set_property -dict {PACKAGE_PIN BP49 IOSTANDARD LVCMOS18} [get_ports exit_o[47]]
set_property -dict {PACKAGE_PIN BP48 IOSTANDARD LVCMOS18} [get_ports exit_o[46]]
set_property -dict {PACKAGE_PIN BN51 IOSTANDARD LVCMOS18} [get_ports exit_o[45]]
set_property -dict {PACKAGE_PIN BN50 IOSTANDARD LVCMOS18} [get_ports exit_o[44]]
set_property -dict {PACKAGE_PIN BN49 IOSTANDARD LVCMOS18} [get_ports exit_o[43]]
set_property -dict {PACKAGE_PIN BM48 IOSTANDARD LVCMOS18} [get_ports exit_o[42]]
set_property -dict {PACKAGE_PIN BM50 IOSTANDARD LVCMOS18} [get_ports exit_o[41]]
set_property -dict {PACKAGE_PIN BM49 IOSTANDARD LVCMOS18} [get_ports exit_o[40]]
set_property -dict {PACKAGE_PIN BM52 IOSTANDARD LVCMOS18} [get_ports exit_o[39]]
set_property -dict {PACKAGE_PIN BL51 IOSTANDARD LVCMOS18} [get_ports exit_o[38]]
set_property -dict {PACKAGE_PIN BL53 IOSTANDARD LVCMOS18} [get_ports exit_o[37]]
set_property -dict {PACKAGE_PIN BL52 IOSTANDARD LVCMOS18} [get_ports exit_o[36]]
set_property -dict {PACKAGE_PIN BK49 IOSTANDARD LVCMOS18} [get_ports exit_o[35]]
set_property -dict {PACKAGE_PIN BK48 IOSTANDARD LVCMOS18} [get_ports exit_o[34]]
set_property -dict {PACKAGE_PIN BK51 IOSTANDARD LVCMOS18} [get_ports exit_o[33]]
set_property -dict {PACKAGE_PIN BK50 IOSTANDARD LVCMOS18} [get_ports exit_o[32]]
set_property -dict {PACKAGE_PIN BJ49 IOSTANDARD LVCMOS18} [get_ports exit_o[31]]
set_property -dict {PACKAGE_PIN BJ48 IOSTANDARD LVCMOS18} [get_ports exit_o[30]]
set_property -dict {PACKAGE_PIN BJ47 IOSTANDARD LVCMOS18} [get_ports exit_o[29]]
set_property -dict {PACKAGE_PIN BH47 IOSTANDARD LVCMOS18} [get_ports exit_o[28]]
set_property -dict {PACKAGE_PIN BJ51 IOSTANDARD LVCMOS18} [get_ports exit_o[27]]
set_property -dict {PACKAGE_PIN BH51 IOSTANDARD LVCMOS18} [get_ports exit_o[26]]
set_property -dict {PACKAGE_PIN BH50 IOSTANDARD LVCMOS18} [get_ports exit_o[25]]
set_property -dict {PACKAGE_PIN BH49 IOSTANDARD LVCMOS18} [get_ports exit_o[24]]
set_property -dict {PACKAGE_PIN BJ53 IOSTANDARD LVCMOS18} [get_ports exit_o[23]]
set_property -dict {PACKAGE_PIN BJ52 IOSTANDARD LVCMOS18} [get_ports exit_o[22]]
set_property -dict {PACKAGE_PIN BH52 IOSTANDARD LVCMOS18} [get_ports exit_o[21]]
set_property -dict {PACKAGE_PIN BG52 IOSTANDARD LVCMOS18} [get_ports exit_o[20]]
set_property -dict {PACKAGE_PIN BK54 IOSTANDARD LVCMOS18} [get_ports exit_o[19]]
set_property -dict {PACKAGE_PIN BK53 IOSTANDARD LVCMOS18} [get_ports exit_o[18]]
set_property -dict {PACKAGE_PIN BJ54 IOSTANDARD LVCMOS18} [get_ports exit_o[17]]
set_property -dict {PACKAGE_PIN BH54 IOSTANDARD LVCMOS18} [get_ports exit_o[16]]
set_property -dict {PACKAGE_PIN BG54 IOSTANDARD LVCMOS18} [get_ports exit_o[15]]
set_property -dict {PACKAGE_PIN BG53 IOSTANDARD LVCMOS18} [get_ports exit_o[14]]
set_property -dict {PACKAGE_PIN BE54 IOSTANDARD LVCMOS18} [get_ports exit_o[13]]
set_property -dict {PACKAGE_PIN BE53 IOSTANDARD LVCMOS18} [get_ports exit_o[12]]
set_property -dict {PACKAGE_PIN BG49 IOSTANDARD LVCMOS18} [get_ports exit_o[11]]
set_property -dict {PACKAGE_PIN BG48 IOSTANDARD LVCMOS18} [get_ports exit_o[10]]
set_property -dict {PACKAGE_PIN BG50 IOSTANDARD LVCMOS18} [get_ports exit_o[9]]
set_property -dict {PACKAGE_PIN BF50 IOSTANDARD LVCMOS18} [get_ports exit_o[8]]
set_property -dict {PACKAGE_PIN BF52 IOSTANDARD LVCMOS18} [get_ports exit_o[7]]
set_property -dict {PACKAGE_PIN BF51 IOSTANDARD LVCMOS18} [get_ports exit_o[6]]
set_property -dict {PACKAGE_PIN BF48 IOSTANDARD LVCMOS18} [get_ports exit_o[5]]
set_property -dict {PACKAGE_PIN BF47 IOSTANDARD LVCMOS18} [get_ports exit_o[4]]
set_property -dict {PACKAGE_PIN BE50 IOSTANDARD LVCMOS18} [get_ports exit_o[3]]
set_property -dict {PACKAGE_PIN BE49 IOSTANDARD LVCMOS18} [get_ports exit_o[2]]
set_property -dict {PACKAGE_PIN BE51 IOSTANDARD LVCMOS18} [get_ports exit_o[1]]
set_property -dict {PACKAGE_PIN BD51 IOSTANDARD LVCMOS18} [get_ports exit_o[0]]

## CLK
set_property -dict {PACKAGE_PIN BJ24 IOSTANDARD LVCMOS18} [get_ports clk_i]

## RESET
set_property -dict {PACKAGE_PIN BH26 IOSTANDARD LVCMOS18} [get_ports rst_ni]

## UART
set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS18} [get_ports rx_i]
set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS18} [get_ports tx_o]

#set_property -dict {PACKAGE_PIN A28 IOSTANDARD LVCMOS18} [get_ports tx_o]
#set_property -dict {PACKAGE_PIN B33 IOSTANDARD LVCMOS18} [get_ports rx_i]


5 changes: 5 additions & 0 deletions fpga/scripts/run.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,5 @@
# read_verilog -sv {../src/ara_0/fpga/src/xcvu9p.svh }
# set file "../src/ara_0/fpga/src/xcvu9p.svh"

set_property is_global_include true [get_files xcvu9p.svh]
set_property is_global_include true [get_files xcu280.svh]
1 change: 1 addition & 0 deletions fpga/scripts/xpm_rams.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
44 changes: 44 additions & 0 deletions fpga/src/clk_gen.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,44 @@
`default_nettype none
module vcu9p_clock_gen
(input wire i_clk,
output wire o_clk,
output reg o_rst);

wire clkfb;
wire locked;
reg locked_r;

MMCME4_ADV
#(.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (48.000),
.CLKOUT0_DIVIDE_F (75.0),
.CLKIN1_PERIOD (8.0), //125MHz
.STARTUP_WAIT ("FALSE"))
mmcm
(.CLKFBOUT (clkfb),
.CLKFBOUTB (),
.CLKOUT0 (o_clk),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN1 (i_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.LOCKED (locked),
.PWRDWN (1'b0),
.RST (1'b0),
.CLKFBIN (clkfb));

always @(posedge o_clk) begin
locked_r <= locked;
o_rst <= !locked_r;
end

endmodule
23 changes: 23 additions & 0 deletions fpga/src/xcu280.svh
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
// Description: Set global FPGA degines
// Author: Elisabeth Humblet [email protected]

`define xcu280

//=============================================================================
// CVA6 Configurations
//=============================================================================
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE 1

`define RVV_ARIANE 1

//=============================================================================
// Ara Configurations
//=============================================================================
`define NrLanes 4
`define VLEN 4096
23 changes: 23 additions & 0 deletions fpga/src/xcvu9p.svh
Original file line number Diff line number Diff line change
@@ -0,0 +1,23 @@
// Description: Set global FPGA degines
// Author: MohammadHossein AskariHemmat [email protected]

`define xcvu9p

//=============================================================================
// CVA6 Configurations
//=============================================================================
`define ARIANE_DATA_WIDTH 64
// Instantiate protocl checker
// `define PROTOCOL_CHECKER
// write-back cache
// `define WB_DCACHE
// write-through cache
`define WT_DCACHE 1

`define RVV_ARIANE 1

//=============================================================================
// Ara Configurations
//=============================================================================
`define NrLanes 4
`define VLEN 4096
118 changes: 118 additions & 0 deletions fpga/src/xilinx_ara_soc.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,118 @@
// Copyright 2022 ETH Zurich and University of Bologna and Polytechnique Montreal.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51
//
// Author: MohammadHossein AskariHemmat <[email protected]>
// Description:
// Ara's FPGA based SoC, containing:
// - ara_soc:
// - ara
// - L2 Cache
// - cva6/ariane
// - peripherals:
// - uart (wip)
// - jtag (wip)

module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
// Number of parallel vector lanes.
parameter int unsigned NrLanes = 4,
// Support for floating-point data types
parameter fpu_support_e FPUSupport = FPUSupportHalfSingleDouble,
// AXI Interface
parameter int unsigned AxiDataWidth = 32*NrLanes,
parameter int unsigned AxiAddrWidth = 64,
parameter int unsigned AxiUserWidth = 1,
parameter int unsigned AxiIdWidth = 5,
// Main memory
parameter int unsigned L2NumWords = 2**15,
// Dependant parameters. DO NOT CHANGE!
localparam type axi_data_t = logic [AxiDataWidth-1:0],
localparam type axi_strb_t = logic [AxiDataWidth/8-1:0],
localparam type axi_addr_t = logic [AxiAddrWidth-1:0],
localparam type axi_user_t = logic [AxiUserWidth-1:0],
localparam type axi_id_t = logic [AxiIdWidth-1:0]
) (
input logic clk_i,
input logic rst_ni,
output logic [63:0] exit_o,
// Scan chain
// UART
input logic rx_i,
output logic tx_o
);


/*************
* Signals *
*************/

// UART
logic uart_penable;
logic uart_pwrite;
logic [31:0] uart_paddr;
logic uart_psel;
logic [31:0] uart_pwdata;
logic [31:0] uart_prdata;
logic uart_pready;
logic uart_pslverr;

//////////////////////
// Ara SoC //
//////////////////////

ara_soc #(
.NrLanes (NrLanes ),
.AxiAddrWidth(AxiAddrWidth ),
.AxiDataWidth(AxiDataWidth ),
.AxiIdWidth (AxiIdWidth ),
.AxiUserWidth(AxiUserWidth ),
.L2NumWords (L2NumWords )
) i_ara_soc (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
.exit_o (exit_o ),
.scan_enable_i (1'b0 ),
.scan_data_i (1'b0 ),
.scan_data_o (/* Unused */),
// UART
.uart_penable_o(uart_penable),
.uart_pwrite_o (uart_pwrite ),
.uart_paddr_o (uart_paddr ),
.uart_psel_o (uart_psel ),
.uart_pwdata_o (uart_pwdata ),
.uart_prdata_i (uart_prdata ),
.uart_pready_i (uart_pready ),
.uart_pslverr_i(uart_pslverr)
);
//////////////////////
// Peripherals //
//////////////////////

//////////////////////
// UART //
//////////////////////
apb_uart i_apb_uart (
.CLK ( clk_i ),
.RSTN ( rst_ni ),
.PSEL ( uart_psel ),
.PENABLE ( uart_penable ),
.PWRITE ( uart_pwrite ),
.PADDR ( uart_paddr[4:2] ),
.PWDATA ( uart_pwdata ),
.PRDATA ( uart_prdata ),
.PREADY ( uart_pready ),
.PSLVERR ( uart_pslverr ),
.INT ( ),
.OUT1N ( ),
.OUT2N ( ),
.RTSN ( ),
.DTRN ( ),
.CTSN ( 1'b0 ),
.DSRN ( 1'b0 ),
.DCDN ( 1'b0 ),
.RIN ( 1'b0 ),
.SIN ( rx_i ),
.SOUT ( tx_o )
);

endmodule : xilinx_ara_soc
1 change: 1 addition & 0 deletions hardware/deps/apb_uart
Submodule apb_uart added at b61453