[fpga] 🎨 Remove trailing white spaces

pulp-platform · Sep 20, 2022 · cdf9593 · cdf9593
1 parent 7e0a8ad
commit cdf9593
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Showing 2 changed files with 9 additions and 13 deletions.
diff --git a/ara.core b/ara.core
@@ -43,10 +43,8 @@ filesets:
             - hardware/deps/axi/src/axi_serializer.sv
             - hardware/deps/axi/src/axi_sim_mem.sv
             - hardware/deps/axi/src/axi_dw_downsizer.sv
-
             - hardware/deps/cva6/include/riscv_pkg.sv
             - hardware/deps/cva6/include/instr_tracer_pkg.sv
-
             - hardware/deps/cva6/src/riscv-dbg/src/dm_pkg.sv
             - hardware/deps/cva6/src/fpu/src/fpnew_pkg.sv
             - hardware/deps/cva6/include/ariane_pkg.sv
@@ -225,7 +223,6 @@ filesets:
             - hardware/deps/cva6/src/util/instr_tracer.sv
             - hardware/deps/cva6/src/util/ex_trace_item.svh: {is_include_file: true}
             - hardware/deps/cva6/src/util/instr_trace_item.svh: {is_include_file: true}
-
             - hardware/deps/apb_uart/src/slib_clock_div.sv
             - hardware/deps/apb_uart/src/slib_counter.sv
             - hardware/deps/apb_uart/src/slib_edge_detect.sv
@@ -331,4 +328,3 @@ parameters:
         datatype  : file
         default   : apps/bin/helloworld_2
         paramtype : plusarg
-
diff --git a/fpga/src/xilinx_ara_soc.sv b/fpga/src/xilinx_ara_soc.sv
@@ -14,8 +14,8 @@
 //          - jtag (wip)
 
 module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
-    // RVV Parameters
-    parameter  int           unsigned NrLanes      = 4,                          // Number of parallel vector lanes.
+    // Number of parallel vector lanes.
+    parameter  int           unsigned NrLanes      = 4,
     // Support for floating-point data types
     parameter  fpu_support_e          FPUSupport   = FPUSupportHalfSingleDouble,
     // AXI Interface
@@ -37,8 +37,8 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
     output logic [63:0] exit_o,
     // Scan chain
     // UART
-    input  logic       rx_i            ,
-    output logic       tx_o              
+    input  logic       rx_i,
+    output logic       tx_o
     );
 
 
@@ -102,11 +102,11 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
     .PRDATA  ( uart_prdata     ),
     .PREADY  ( uart_pready     ),
     .PSLVERR ( uart_pslverr    ),
-    .INT     (                 ), // no interrupts 
-    .OUT1N   (                 ), // keep open
-    .OUT2N   (                 ), // keep open
-    .RTSN    (                 ), // no flow control
-    .DTRN    (                 ), // no flow control
+    .INT     (                 ),
+    .OUT1N   (                 ),
+    .OUT2N   (                 ),
+    .RTSN    (                 ),
+    .DTRN    (                 ),
     .CTSN    ( 1'b0            ),
     .DSRN    ( 1'b0            ),
     .DCDN    ( 1'b0            ),