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[hardware] Set ara's cache size from top level
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hossein1387 committed Sep 19, 2022
1 parent 3c3cddb commit 7e0a8ad
Showing 1 changed file with 2 additions and 1 deletion.
3 changes: 2 additions & 1 deletion fpga/src/xilinx_ara_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -65,7 +65,8 @@ module xilinx_ara_soc import axi_pkg::*; import ara_pkg::*; #(
.AxiAddrWidth(AxiAddrWidth ),
.AxiDataWidth(AxiDataWidth ),
.AxiIdWidth (AxiIdWidth ),
.AxiUserWidth(AxiUserWidth )
.AxiUserWidth(AxiUserWidth ),
.L2NumWords (L2NumWords )
) i_ara_soc (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
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