Design Document, add ID_STAGE description #1832
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| The compressed_decoder module decompresses all the compressed | ||
| instructions taking a 16-bit compressed instruction and expanding it | ||
| to its 32-bit equivalent. | ||
| All compressed instructions have a 32-bit equivalent. |
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This is true with CVA6 (so no change is required).
FYI: This is no more true globally for the RISC-V ISA as the Zcmp extension includes instructions like push and pop that are expanded as series of 32-bit instructions. And Zcmt instructions have no equivalent 32-bits instructions.
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| Memory Management Unit |
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MMU in the embedded CV32A65X?
FYI, PlanV is upgrading the MMU documentation to expand with Sv39 and and Sv39x4, as part of the MMU unification.
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MMU removed from 65X DD
| @@ -26,7 +26,12 @@ At least 6 cycles are needed to execute one instruction. | |||
| Connection with other sub-systems | |||
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At line 18, missing period at the end of the sentence.
At line 21 "The processor is single issue", no more true for CV32A65X.
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Thanks for the feedback, I will fix in a next PR.
| @@ -15,7 +15,7 @@ | |||
| * - Signal | |||
| - IO | |||
| - Description | |||
| - Connection | |||
| - connexion | |||
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"Connexion" in French, "connection" in English. This is counter-intuitive.
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Oeufs corses ! Fixed
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Add chapters corresponding to the N-1 CVA6 hierarchy.
Add block diagrams.
Add ID_STAGE first description, to be fine-tuned.