Design Document, add ID_STAGE description

core/commit_stage.sv

@@ -36,13 +36,13 @@ module commit_stage
     input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     // Acknowledge that we are indeed committing - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
-    // Register file write address - ID_STAGE
+    // Register file write address - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][4:0] waddr_o,
-    // Register file write data - ID_STAGE
+    // Register file write data - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0] wdata_o,
-    // Register file write enable - ID_STAGE
+    // Register file write enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_gpr_o,
-    // Floating point register enable - ID_STAGE
+    // Floating point register enable - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_o,
     // Result of AMO operation - CACHE
     input amo_resp_t amo_resp_i,

core/compressed_decoder.sv

@@ -22,9 +22,13 @@
 module compressed_decoder #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
+    // Input instruction coming from fetch stage - FRONTEND
     input  logic [31:0] instr_i,
+    // Output instruction in uncompressed format - decoder
     output logic [31:0] instr_o,
+    // Input instruction is illegal - decoder
     output logic        illegal_instr_o,
+    // Output instruction is compressed - decoder
     output logic        is_compressed_o
 );
 

core/decoder.sv

@@ -24,28 +24,48 @@ module decoder
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
-    input logic debug_req_i,  // external debug request
-    input logic [riscv::VLEN-1:0] pc_i,  // PC from IF
-    input logic is_compressed_i,  // is a compressed instruction
-    input logic [15:0] compressed_instr_i,  // compressed form of instruction
-    input logic is_illegal_i,  // illegal compressed instruction
-    input logic [31:0] instruction_i,  // instruction from IF
+    // Debug (async) request - SUBSYSTEM
+    input logic debug_req_i,
+    // PC from fetch stage - FRONTEND
+    input logic [riscv::VLEN-1:0] pc_i,
+    // Is a compressed instruction - compressed_decoder
+    input logic is_compressed_i,
+    // Compressed form of instruction - FRONTEND
+    input logic [15:0] compressed_instr_i,
+    // Illegal compressed instruction - compressed_decoder
+    input logic is_illegal_i,
+    // Instruction from fetch stage - FRONTEND
+    input logic [31:0] instruction_i,
+    // Is a branch predict instruction - FRONTEND
     input branchpredict_sbe_t branch_predict_i,
-    input exception_t ex_i,  // if an exception occured in if
-    input logic [1:0] irq_i,  // external interrupt
-    input irq_ctrl_t irq_ctrl_i,  // interrupt control and status information from CSRs
-    // From CSR
-    input riscv::priv_lvl_t priv_lvl_i,  // current privilege level
-    input logic debug_mode_i,  // we are in debug mode
-    input riscv::xs_t fs_i,  // floating point extension status
-    input logic [2:0] frm_i,  // floating-point dynamic rounding mode
-    input riscv::xs_t vs_i,  // vector extension status
-    input logic tvm_i,  // trap virtual memory
-    input logic tw_i,  // timeout wait
-    input logic tsr_i,  // trap sret
-    output scoreboard_entry_t instruction_o,  // scoreboard entry to scoreboard
-    output logic [31:0] orig_instr_o,  // instruction opcode to issue read operand for CVXIF
-    output logic is_control_flow_instr_o  // this instruction will change the control flow
+    // If an exception occured in fetch stage - FRONTEND
+    input exception_t ex_i,
+    // Level sensitive (async) interrupts - SUBSYSTEM
+    input logic [1:0] irq_i,
+    // Interrupt control status - CSR_REGFILE
+    input irq_ctrl_t irq_ctrl_i,
+    // Current privilege level - CSR_REGFILE
+    input riscv::priv_lvl_t priv_lvl_i,
+    // Is debug mode - CSR_REGFILE
+    input logic debug_mode_i,
+    // Floating point extension status - CSR_REGFILE
+    input riscv::xs_t fs_i,
+    // Floating-point dynamic rounding mode - CSR_REGFILE
+    input logic [2:0] frm_i,
+    // Vector extension status - CSR_REGFILE
+    input riscv::xs_t vs_i,
+    // Trap virtual memory - CSR_REGFILE
+    input logic tvm_i,
+    // Timeout wait - CSR_REGFILE
+    input logic tw_i,
+    // Trap sret - CSR_REGFILE
+    input logic tsr_i,
+    // Instruction to be added to scoreboard entry - ISSUE_STAGE
+    output scoreboard_entry_t instruction_o,
+    // Instruction - ISSUE_STAGE
+    output logic [31:0] orig_instr_o,
+    // Is a control flow instruction - ISSUE_STAGE
+    output logic is_control_flow_instr_o
 );
   logic illegal_instr;
   logic illegal_instr_bm;

core/ex_stage.sv

@@ -28,131 +28,131 @@ module ex_stage
     input logic flush_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic debug_mode_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // rs1 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs1_forwarding_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // rs2 forwarding - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] rs2_forwarding_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FU data useful to execute instruction - ISSUE_STAGE
     input fu_data_t fu_data_i,
-    // PC of the current instruction - ID_STAGE
+    // PC of the current instruction - ISSUE_STAGE
     input logic [riscv::VLEN-1:0] pc_i,
-    // Report whether isntruction is compressed - ID_STAGE
+    // Report whether isntruction is compressed - ISSUE_STAGE
     input logic is_compressed_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output riscv::xlen_t flu_result_o,
-    // ID of the scoreboard entry at which a=to write back - ID_STAGE
+    // ID of the scoreboard entry at which a=to write back - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] flu_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // TO_BE_COMPLETED - ISSUE_STAGE
     output exception_t flu_exception_o,
-    // FLU is ready - ID_STAGE
+    // FLU is ready - ISSUE_STAGE
     output logic flu_ready_o,
-    // FLU result is valid - ID_STAGE
+    // FLU result is valid - ISSUE_STAGE
     output logic flu_valid_o,
-    // ALU result is valid - ID_STAGE
+    // ALU instruction is valid - ISSUE_STAGE
     input logic alu_valid_i,
-    // Branch unit result is valid - ID_STAGE
+    // Branch unit instruction is valid - ISSUE_STAGE
     input logic branch_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Information of branch prediction - ISSUE_STAGE
     input branchpredict_sbe_t branch_predict_i,
-    // The branch engine uses the write back from the ALU - CONTROLLER PERF_COUNTER FRONTEND ISSUE_STAGE
+    // The branch engine uses the write back from the ALU - several_modules
     output bp_resolve_t resolved_branch_o,
-    // ID signaling that we resolved the branch - ID_STAGE
+    // Signaling that we resolved the branch - ISSUE_STAGE
     output logic resolve_branch_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CSR instruction is valid - ISSUE_STAGE
     input logic csr_valid_i,
-    // TO_BE_COMPLETED - CSR_REGISTERS
+    // CSR address to write - COMMIT_STAGE
     output logic [11:0] csr_addr_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic csr_commit_i,
-    // MULT result is valid - ID_STAGE
+    // MULT instruction is valid - ISSUE_STAGE
     input logic mult_valid_i,
-    // FU is ready - ID_STAGE
+    // LSU is ready - ISSUE_STAGE
     output logic lsu_ready_o,
-    // LSU result is valid - ID_STAGE
+    // LSU instruction is valid - ISSUE_STAGE
     input logic lsu_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load result is valid - ISSUE_STAGE
     output logic load_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load result valid - ISSUE_STAGE
     output riscv::xlen_t load_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Load instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] load_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Exception generated by load instruction - ISSUE_STAGE
     output exception_t load_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store result is valid - ISSUe_STAGE
     output logic store_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store result - ISSUE_STAGE
     output riscv::xlen_t store_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Store instruction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] store_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // Exception generated by store instruction - ISSUE_STAGE
     output exception_t store_exception_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic lsu_commit_i,
-    // Commit queue is ready to accept another commit request - COMMIT_STAGE
+    // Commit queue ready to accept another commit request - COMMIT_STAGE
     output logic lsu_commit_ready_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic [TRANS_ID_BITS-1:0] commit_tran_id_i,
     // TO_BE_COMPLETED - ACC_DISPATCHER
     input logic stall_st_pending_i,
     // TO_BE_COMPLETED - COMMIT_STAGE
     output logic no_st_pending_o,
-    // TO_BE_COMPLETED - COMMIT_STAGE
+    // Atomic result is valid - COMMIT_STAGE
     input logic amo_valid_commit_i,
-    // FU is ready - ID_STAGE
+    // FU is ready - ISSUE_STAGE
     output logic fpu_ready_o,
-    // Output is ready - ID_STAGE
+    // FPU instruction is ready - ISSUE_STAGE
     input logic fpu_valid_i,
-    // report FP format - ID_STAGE
+    // FPU format - ISSUE_STAGE
     input logic [1:0] fpu_fmt_i,
-    // FP rm - ID_STAGE
+    // FPU rm - ISSUE_STAGE
     input logic [2:0] fpu_rm_i,
-    // FP frm - ID_STAGE
+    // FPU frm - ISSUE_STAGE
     input logic [2:0] fpu_frm_i,
-    // FP precision control - CSR_REGFILE
+    // FPU precision control - CSR_REGFILE
     input logic [6:0] fpu_prec_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] fpu_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU result - ISSUE_STAGE
     output riscv::xlen_t fpu_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU valid - ISSUE_STAGE
     output logic fpu_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // FPU exception - ISSUE_STAGE
     output exception_t fpu_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF instruction is valid - ISSUE_STAGE
     input logic x_valid_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF is ready - ISSUE_STAGE
     output logic x_ready_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // undecoded instruction - ISSUE_STAGE
     input logic [31:0] x_off_instr_i,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF transaction ID - ISSUE_STAGE
     output logic [TRANS_ID_BITS-1:0] x_trans_id_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF exception - ISSUE_STAGE
     output exception_t x_exception_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result - ISSUE_STAGE
     output riscv::xlen_t x_result_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF result valid - ISSUE_STAGE
     output logic x_valid_o,
-    // TO_BE_COMPLETED - ID_STAGE
+    // CVXIF write enable - ISSUE_STAGE
     output logic x_we_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF request - SUBSYSTEM
     output cvxif_pkg::cvxif_req_t cvxif_req_o,
-    // TO_BE_COMPLETED - SUBSYSTEM
+    // CVXIF response - SUBSYSTEM
     input cvxif_pkg::cvxif_resp_t cvxif_resp_i,
-    // TO_BE_COMPLETED - ACC_DISPATCHER
+    // accelerate port result is valid - ACC_DISPATCHER
     input logic acc_valid_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic enable_translation_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic en_ld_st_translation_i,
     // TO_BE_COMPLETED - CONTROLLER
     input logic flush_tlb_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Privilege mode - CSR_REGFILE
     input riscv::priv_lvl_t priv_lvl_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Privilege level at which load and stores should happen - CSR_REGFILE
     input riscv::priv_lvl_t ld_st_priv_lvl_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Supervisor user memory - CSR_REGFILE
     input logic sum_i,
-    // TO_BE_COMPLETED - CSR_REGFILE
+    // Make executable readable - CSR_REGFILE
     input logic mxr_i,
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic [riscv::PPNW-1:0] satp_ppn_i,
@@ -183,9 +183,9 @@ module ex_stage
     input riscv::pmpcfg_t [15:0] pmpcfg_i,
     // Report the PMP addresses - CSR_REGFILE
     input logic [15:0][riscv::PLEN-3:0] pmpaddr_i,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output lsu_ctrl_t rvfi_lsu_ctrl_o,
-    // Information dedicated to RVFI - SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output [riscv::PLEN-1:0] rvfi_mem_paddr_o
 );
 

core/id_stage.sv

@@ -32,35 +32,35 @@ module id_stage #(
     output logic fetch_entry_ready_o,
     // Handshake's data between decode and issue - ISSUE
     output ariane_pkg::scoreboard_entry_t issue_entry_o,
-    // instruction value - ISSUE
+    // Instruction value - ISSUE
     output logic [31:0] orig_instr_o,
     // Handshake's valid between decode and issue - ISSUE
     output logic issue_entry_valid_o,
     // Report if instruction is a control flow instruction - ISSUE
     output logic is_ctrl_flow_o,
     // Handshake's acknowlege between decode and issue - ISSUE
     input logic issue_instr_ack_i,
-    // Information dedicated to RVFI- SUBSYSTEM
+    // Information dedicated to RVFI - RVFI
     output logic rvfi_is_compressed_o,
-    // Report current privilege level - CSR
+    // Current privilege level - CSR_REGFILE
     input riscv::priv_lvl_t priv_lvl_i,
-    // Report floating point extension status - CSR
+    // Floating point extension status - CSR_REGFILE
     input riscv::xs_t fs_i,
-    // Report floating point dynamic rounding mode - CSR
+    // Floating point dynamic rounding mode - CSR_REGFILE
     input logic [2:0] frm_i,
-    // Report vector extension status - CSR
+    // Vector extension status - CSR_REGFILE
     input riscv::xs_t vs_i,
     // Level sensitive (async) interrupts - SUBSYSTEM
     input logic [1:0] irq_i,
-    // TBD - CSR
+    // Interrupt control status - CSR_REGFILE
     input ariane_pkg::irq_ctrl_t irq_ctrl_i,
-    // Report if current mode is debug - CSR
+    // Is current mode debug ? - CSR_REGFILE
     input logic debug_mode_i,
-    // TBD - CSR
+    // Trap virtual memory - CSR_REGFILE
     input logic tvm_i,
-    // TBD - CSR
+    // Timeout wait - CSR_REGFILE
     input logic tw_i,
-    // TBD- CSR
+    // Trap sret - CSR_REGFILE
     input logic tsr_i
 );
   // ID/ISSUE register stage

core/instr_realign.sv

@@ -43,7 +43,7 @@ module instr_realign
     output logic [INSTR_PER_FETCH-1:0] valid_o,
     // Instruction address - FRONTEND
     output logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0] addr_o,
-    // Instruction - instr_scan, instr_queue
+    // Instruction - instr_scan&instr_queue
     output logic [INSTR_PER_FETCH-1:0][31:0] instr_o
 );
   // as a maximum we support a fetch width of 64-bit, hence there can be 4 compressed instructions