Design Document, add ID_STAGE description

core/compressed_decoder.sv

@@ -22,9 +22,13 @@
 module compressed_decoder #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
+    // Input instruction which can be compressed - FRONTEND
     input  logic [31:0] instr_i,
+    // Output instruction which is uncompressed - ID_STAGE
     output logic [31:0] instr_o,
+    // Illegal instruction exception - TO_BE_COMPLETED
     output logic        illegal_instr_o,
+    // report if instruction is compressed - TO_BE_COMPLETED
     output logic        is_compressed_o
 );
 

core/decoder.sv

@@ -24,28 +24,48 @@ module decoder
 #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
 ) (
-    input logic debug_req_i,  // external debug request
-    input logic [riscv::VLEN-1:0] pc_i,  // PC from IF
-    input logic is_compressed_i,  // is a compressed instruction
-    input logic [15:0] compressed_instr_i,  // compressed form of instruction
-    input logic is_illegal_i,  // illegal compressed instruction
-    input logic [31:0] instruction_i,  // instruction from IF
+    // External debug request - TO_BE_COMPLETED
+    input logic debug_req_i,
+    // PC from IF - TO_BE_COMPLETED
+    input logic [riscv::VLEN-1:0] pc_i,
+    // Is a compressed instruction - TO_BE_COMPLETED
+    input logic is_compressed_i,
+    // Compressed form of instruction - TO_BE_COMPLETED
+    input logic [15:0] compressed_instr_i,
+    // Illegal compressed instruction - TO_BE_COMPLETED
+    input logic is_illegal_i,
+    // Instruction from IF - TO_BE_COMPLETED
+    input logic [31:0] instruction_i,
+    // TO_BE_COMPLETED - TO_BE_COMPLETED
     input branchpredict_sbe_t branch_predict_i,
-    input exception_t ex_i,  // if an exception occured in if
-    input logic [1:0] irq_i,  // external interrupt
-    input irq_ctrl_t irq_ctrl_i,  // interrupt control and status information from CSRs
-    // From CSR
-    input riscv::priv_lvl_t priv_lvl_i,  // current privilege level
-    input logic debug_mode_i,  // we are in debug mode
-    input riscv::xs_t fs_i,  // floating point extension status
-    input logic [2:0] frm_i,  // floating-point dynamic rounding mode
-    input riscv::xs_t vs_i,  // vector extension status
-    input logic tvm_i,  // trap virtual memory
-    input logic tw_i,  // timeout wait
-    input logic tsr_i,  // trap sret
-    output scoreboard_entry_t instruction_o,  // scoreboard entry to scoreboard
-    output logic [31:0] orig_instr_o,  // instruction opcode to issue read operand for CVXIF
-    output logic is_control_flow_instr_o  // this instruction will change the control flow
+    // If an exception occured in if - TO_BE_COMPLETED
+    input exception_t ex_i,
+    // External interrupt - TO_BE_COMPLETED
+    input logic [1:0] irq_i,
+    // Interrupt control and status information from CSRs - TO_BE_COMPLETED
+    input irq_ctrl_t irq_ctrl_i,
+    // Current privilege level - CSR_REGFILE
+    input riscv::priv_lvl_t priv_lvl_i,
+    // We are in debug mode - CSR_REGFILE
+    input logic debug_mode_i,
+    // Floating point extension status - CSR_REGFILE
+    input riscv::xs_t fs_i,
+    // Floating-point dynamic rounding mode - CSR_REGFILE
+    input logic [2:0] frm_i,
+    // Vector extension status - CSR_REGFILE
+    input riscv::xs_t vs_i,
+    // Trap virtual memory - CSR_REGFILE
+    input logic tvm_i,
+    // Timeout wait - CSR_REGFILE
+    input logic tw_i,
+    // Trap sret - CSR_REGFILE
+    input logic tsr_i,
+    // Scoreboard entry to scoreboard - COMMIT_STAGE
+    output scoreboard_entry_t instruction_o,
+    // Instruction opcode to issue read operand for CVXIF - TO_BE_COMPLETED
+    output logic [31:0] orig_instr_o,
+    // This instruction will change the control flow - TO_BE_COMPLETED
+    output logic is_control_flow_instr_o
 );
   logic illegal_instr;
   logic illegal_instr_bm;

docs/01_cva6_user/RISCV_Instructions.rst

@@ -20,8 +20,8 @@
 
 *This chapter is applicable to all configurations.*
 
-RISC-V Instructions
-===================
+CVA6 RISC-V Instructions
+========================
 
 Introduction
 ------------------

docs/04_cv32a65x_design/source/CSRs.rst

@@ -12,7 +12,7 @@ CSR
 ===
 
 .. toctree::
-   :hidden:
+   :maxdepth: 1
 
    csr_list
    csr

docs/04_cv32a65x_design/source/architecture.rst

@@ -12,23 +12,27 @@
 Architecture and Modules
 ========================
 
-The CV32A6 v0.1.0 subsystem is composed of 8 modules.
+The CV32A65X is fully synthesizable. It has been designed mainly for ASIC designs, but FPGA synthesis is supported as well.
+
+For ASIC synthesis, the whole design is completely synchronous and uses positive-edge triggered flip-flops. The core occupies an area of about 80 kGE. The clock frequency can be more than 1GHz depending of technology.
+
+The CV32A65X subsystem is composed of 8 modules.
 
 .. figure:: ../images/subsystems.png
    :name: CV32A6 v0.1.0 modules
    :align: center
    :alt:
 
-   CV32A6 v0.1.0 modules
+   CV32A65X modules
 
 Connections between modules are illustrated in the following block diagram. FRONTEND, DECODE, ISSUE, EXECUTE, COMMIT and CONTROLLER are part of the pipeline. And CACHES implements the instruction and data caches and CSRFILE contains registers.
 
-.. figure:: ../images/CVA6_subsystems.png
-   :name: CVA6 subsystem
+.. figure:: ../images/CV32A65X_subsystems.png
+   :name: CV32A65X subsystem
    :align: center
    :alt:
 
-   CV32A6 v0.1.0 pipeline and modules
+   CV32A65X pipeline and modules
 
 .. toctree::
    :hidden: