Table builder for specification #1814

JeanRochCoulon · 2024-02-07T11:29:40Z

In this MR:

Commit, csr and controller modules are post processed to generate port IO tables in Design Document
Config package to generate the parameter table in Design Document

@jquevremont This PR setup a flow to generate the "parameter configuration" table to be inserted in cv32a65x design documentation. It is generated from RTL.

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/commit_stage.sv

github-actions · 2024-02-07T11:30:35Z

core/csr_regfile.sv

-    input logic time_irq_i,  // Timer threw a interrupt
-    // send a flush request out if a CSR with a side effect has changed (e.g. written)
+    // Subsystem Clock - SUBSYSTEM
+    input logic clk_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic clk_i,

input logic clk_i,

github-actions · 2024-02-07T11:30:35Z

core/csr_regfile.sv

+    // Subsystem Clock - SUBSYSTEM
+    input logic clk_i,
+    // Asynchronous reset active low - SUBSYSTEM
+    input logic rst_ni,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic rst_ni,

input logic rst_ni,

github-actions · 2024-02-07T11:30:35Z

core/csr_regfile.sv

+    // Asynchronous reset active low - SUBSYSTEM
+    input logic rst_ni,
+    // Timer threw a interrupt - SUBSYSTEM
+    input logic time_irq_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic time_irq_i,

input logic time_irq_i,

github-actions · 2024-02-07T11:30:37Z

core/csr_regfile.sv

+    // Current privilege level the CPU is in - EX_STAGE
+    output riscv::priv_lvl_t priv_lvl_o,
+    // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER
+    input  logic [4:0] acc_fflags_ex_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic [4:0] acc_fflags_ex_i,

input logic [ 4:0] acc_fflags_ex_i,

github-actions · 2024-02-07T11:30:37Z

core/csr_regfile.sv

+    // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER
+    input  logic [4:0] acc_fflags_ex_i,
+    // An FP exception from the accelerator occurred - ACC_DISPATCHER
+    input logic acc_fflags_ex_valid_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic acc_fflags_ex_valid_i,

input logic acc_fflags_ex_valid_i,

github-actions · 2024-02-07T11:30:37Z

core/csr_regfile.sv

+    // An FP exception from the accelerator occurred - ACC_DISPATCHER
+    input logic acc_fflags_ex_valid_i,
+    // Floating point extension status - ID_STAGE
+    output riscv::xs_t fs_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output riscv::xs_t fs_o,

output riscv::xs_t fs_o,

github-actions · 2024-02-07T11:30:37Z

core/csr_regfile.sv

+    // Floating point extension status - ID_STAGE
+    output riscv::xs_t fs_o,
+    // Floating-Point Accured Exceptions - COMMIT_STAGE
+    output logic [4:0] fflags_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [4:0] fflags_o,

output logic [ 4:0] fflags_o,

github-actions · 2024-02-07T11:30:37Z

core/csr_regfile.sv

+    // Floating-Point Accured Exceptions - COMMIT_STAGE
+    output logic [4:0] fflags_o,
+    // Floating-Point Dynamic Rounding Mode - EX_STAGE
+    output logic [2:0] frm_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [2:0] frm_o,

output logic [ 2:0] frm_o,

github-actions · 2024-02-07T11:32:50Z

❌ failed run, report available here.

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/ex_stage.sv|162|
core/include/cv32a65x_config_pkg.sv|96|
core/include/cv32a65x_config_pkg.sv|123|
core/include/cv32a65x_config_pkg.sv|128|
core/include/cv32a65x_config_pkg.sv|131|

github-actions · 2024-02-07T11:35:16Z

core/commit_stage.sv

+    // Data to read from CSR - CSR_REGFILE
+    input riscv::xlen_t csr_rdata_i,
+    // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
+    input  exception_t csr_exception_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input exception_t csr_exception_i,

input exception_t csr_exception_i,

github-actions · 2024-02-07T11:35:16Z

core/csr_regfile.sv

+    // Floating-Point Dynamic Rounding Mode - EX_STAGE
+    output logic [2:0] frm_o,
+    // Floating-Point Precision Control - EX_STAGE
+    output logic [6:0] fprec_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [6:0] fprec_o,

output logic [ 6:0] fprec_o,

github-actions · 2024-02-07T11:35:16Z

core/csr_regfile.sv

+    // Floating-Point Precision Control - EX_STAGE
+    output logic [6:0] fprec_o,
+    // Vector extension status - ID_STAGE
+    output riscv::xs_t vs_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output riscv::xs_t vs_o,

output riscv::xs_t vs_o,

github-actions · 2024-02-07T11:35:17Z

core/csr_regfile.sv

+    // Vector extension status - ID_STAGE
+    output riscv::xs_t vs_o,
+    // interrupt management to id stage - ID_STAGE
+    output irq_ctrl_t irq_ctrl_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output irq_ctrl_t irq_ctrl_o,

output irq_ctrl_t irq_ctrl_o,

github-actions · 2024-02-07T11:35:17Z

core/csr_regfile.sv

+    // interrupt management to id stage - ID_STAGE
+    output irq_ctrl_t irq_ctrl_o,
+    // enable VA translation - EX_STAGE
+    output logic en_translation_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic en_translation_o,

output logic en_translation_o,

github-actions · 2024-02-07T11:35:19Z

core/csr_regfile.sv

+    // write data to performance counter module - PERF_COUNTERS
+    output logic [riscv::XLEN-1:0] perf_data_o,
+    // read data from performance counter module - PERF_COUNTERS
+    input logic [riscv::XLEN-1:0] perf_data_i,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

input logic [riscv::XLEN-1:0] perf_data_i,

input logic [ riscv::XLEN-1:0] perf_data_i,

github-actions · 2024-02-07T11:35:19Z

core/csr_regfile.sv

+    output logic [riscv::XLEN-1:0] perf_data_o,
+    // read data from performance counter module - PERF_COUNTERS
+    input logic [riscv::XLEN-1:0] perf_data_i,
+    // TO_BE_COMPLETED - PERF_COUNTERS
    output logic perf_we_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic perf_we_o,

output logic perf_we_o,

github-actions · 2024-02-07T11:35:19Z

core/csr_regfile.sv

-    output riscv::pmpcfg_t [15:0] pmpcfg_o,  // PMP configuration containing pmpcfg for max 16 PMPs
-    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,  // PMP addresses
+    // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
+    output riscv::pmpcfg_t [15:0] pmpcfg_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output riscv::pmpcfg_t [15:0] pmpcfg_o,

output riscv::pmpcfg_t [ 15:0] pmpcfg_o,

github-actions · 2024-02-07T11:35:19Z

core/csr_regfile.sv

+    // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
+    output riscv::pmpcfg_t [15:0] pmpcfg_o,
+    // PMP addresses - ACC_DISPATCHER
+    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,

output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o,

github-actions · 2024-02-07T11:35:19Z

core/csr_regfile.sv

+    output riscv::pmpcfg_t [15:0] pmpcfg_o,
+    // PMP addresses - ACC_DISPATCHER
+    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,
+    // TO_BE_COMPLETED - PERF_COUNTERS
    output logic [31:0] mcountinhibit_o


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [31:0] mcountinhibit_o

output logic [ 31:0] mcountinhibit_o

github-actions

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

core/include/cv32a65x_config_pkg.sv|96|
core/include/cv32a65x_config_pkg.sv|123|
core/include/cv32a65x_config_pkg.sv|128|
core/include/cv32a65x_config_pkg.sv|131|

github-actions · 2024-02-07T11:35:17Z

core/csr_regfile.sv

+    // Floating-Point Dynamic Rounding Mode - EX_STAGE
+    output logic [2:0] frm_o,
+    // Floating-Point Precision Control - EX_STAGE
+    output logic [6:0] fprec_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [6:0] fprec_o,

output logic [ 6:0] fprec_o,

github-actions · 2024-02-07T11:35:17Z

core/csr_regfile.sv

+    // Floating-Point Precision Control - EX_STAGE
+    output logic [6:0] fprec_o,
+    // Vector extension status - ID_STAGE
+    output riscv::xs_t vs_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output riscv::xs_t vs_o,

output riscv::xs_t vs_o,

github-actions · 2024-02-07T11:35:17Z

core/csr_regfile.sv

+    // Vector extension status - ID_STAGE
+    output riscv::xs_t vs_o,
+    // interrupt management to id stage - ID_STAGE
+    output irq_ctrl_t irq_ctrl_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output irq_ctrl_t irq_ctrl_o,

output irq_ctrl_t irq_ctrl_o,

github-actions · 2024-02-07T11:35:18Z

core/csr_regfile.sv

+    // interrupt management to id stage - ID_STAGE
+    output irq_ctrl_t irq_ctrl_o,
+    // enable VA translation - EX_STAGE
+    output logic en_translation_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic en_translation_o,

output logic en_translation_o,

github-actions · 2024-02-07T11:35:18Z

core/csr_regfile.sv

+    // enable VA translation - EX_STAGE
+    output logic en_translation_o,
+    // enable VA translation for load and stores - EX_STAGE
+    output logic en_ld_st_translation_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic en_ld_st_translation_o,

output logic en_ld_st_translation_o,

github-actions · 2024-02-07T11:35:20Z

core/csr_regfile.sv

+    output logic [riscv::XLEN-1:0] perf_data_o,
+    // read data from performance counter module - PERF_COUNTERS
+    input logic [riscv::XLEN-1:0] perf_data_i,
+    // TO_BE_COMPLETED - PERF_COUNTERS
    output logic perf_we_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic perf_we_o,

output logic perf_we_o,

github-actions · 2024-02-07T11:35:20Z

core/csr_regfile.sv

-    output riscv::pmpcfg_t [15:0] pmpcfg_o,  // PMP configuration containing pmpcfg for max 16 PMPs
-    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,  // PMP addresses
+    // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
+    output riscv::pmpcfg_t [15:0] pmpcfg_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output riscv::pmpcfg_t [15:0] pmpcfg_o,

output riscv::pmpcfg_t [ 15:0] pmpcfg_o,

github-actions · 2024-02-07T11:35:20Z

core/csr_regfile.sv

+    // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
+    output riscv::pmpcfg_t [15:0] pmpcfg_o,
+    // PMP addresses - ACC_DISPATCHER
+    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,

output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o,

github-actions · 2024-02-07T11:35:20Z

core/csr_regfile.sv

+    output riscv::pmpcfg_t [15:0] pmpcfg_o,
+    // PMP addresses - ACC_DISPATCHER
+    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,
+    // TO_BE_COMPLETED - PERF_COUNTERS
    output logic [31:0] mcountinhibit_o


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

output logic [31:0] mcountinhibit_o

output logic [ 31:0] mcountinhibit_o

core/ex_stage.sv

github-actions · 2024-02-07T11:37:22Z

core/include/cv32a65x_config_pkg.sv

-      bit'(
-      0
-      ),
+      RVF: bit'(0),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

RVF: bit'(0),

RVF:

bit'(

0

),

github-actions · 2024-02-07T11:37:22Z

core/include/cv32a65x_config_pkg.sv

-      unsigned'(
-      2
-      ),
+      NrNonIdempotentRules: unsigned'(2),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

NrNonIdempotentRules: unsigned'(2),

NrNonIdempotentRules:

unsigned'(

2

),

github-actions · 2024-02-07T11:37:23Z

core/include/cv32a65x_config_pkg.sv

-      1024'(
-      {64'h8000_0000, 64'h1_0000, 64'h0}
-      ),
+      ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),

ExecuteRegionAddrBase:

1024'(

{64'h8000_0000, 64'h1_0000, 64'h0}

),

github-actions · 2024-02-07T11:37:23Z

core/include/cv32a65x_config_pkg.sv

-      unsigned'(
-      1
-      ),
+      NrCachedRegionRules: unsigned'(1),


[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

NrCachedRegionRules: unsigned'(1),

NrCachedRegionRules:

unsigned'(

1

),

github-actions · 2024-02-07T11:37:29Z

❌ failed run, report available here.

github-actions · 2024-02-07T11:37:58Z

❌ failed run, report available here.

github-actions · 2024-02-07T11:40:36Z

❌ failed run, report available here.

github-actions · 2024-02-07T13:56:35Z

❌ failed run, report available here.

Result = 9.07/10

github-actions · 2024-02-08T08:13:25Z

✔️ successful run, report available here.

JeanRochCoulon · 2024-02-08T08:31:32Z

@ASintzoff Can you approve ?

JeanRochCoulon · 2024-02-08T09:53:51Z

This PR has been approved by @ASintzoff internally before PR on Github.

JeanRochCoulon requested review from jquevremont and zarubaf as code owners February 7, 2024 11:29

github-actions bot reviewed Feb 7, 2024

View reviewed changes

JeanRochCoulon changed the title ~~Table builder~~ Table builder for specification Feb 7, 2024

github-actions bot reviewed Feb 7, 2024

View reviewed changes

JeanRochCoulon force-pushed the table_builder branch from e7f1989 to 7b0de6f Compare February 7, 2024 13:52

JeanRochCoulon added 9 commits February 7, 2024 18:28

Generate id_stage, issue_stage, ex_stage port tables

5ce5f32

generate port tabl for commit stage

981f9df

Generate the port table for controller module

0e040de

Generate port table for csr_regfile

ffde467

Generate CV32A65X parameter table in Design Document

0c11bb6

Black refomat

693a4d8

FIx pylint error/warning

228b666

Result = 9.07/10

Fixes from André review

bf422f7

Fix Verible and co

7f5870b

JeanRochCoulon mentioned this pull request Feb 7, 2024

[TASK] Generate parameter configuration specification table from RTL #1793

Closed

1 task

JeanRochCoulon force-pushed the table_builder branch from 2c6e8e3 to 7f5870b Compare February 8, 2024 07:31

JeanRochCoulon merged commit 3f8649e into openhwgroup:master Feb 8, 2024
19 checks passed

JeanRochCoulon deleted the table_builder branch February 8, 2024 09:54

JeanRochCoulon mentioned this pull request Feb 8, 2024

[TASK] Table generation of port specification #1792

Closed

1 task

	input logic [4:0] acc_fflags_ex_i,
	input logic [ 4:0] acc_fflags_ex_i,

	input logic acc_fflags_ex_valid_i,
	input logic acc_fflags_ex_valid_i,

	input exception_t csr_exception_i,
	input exception_t csr_exception_i,

	output logic en_translation_o,
	output logic en_translation_o,

	input logic [riscv::XLEN-1:0] perf_data_i,
	input logic [ riscv::XLEN-1:0] perf_data_i,

	output riscv::pmpcfg_t [15:0] pmpcfg_o,
	output riscv::pmpcfg_t [ 15:0] pmpcfg_o,

	output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,
	output logic [ 15:0][riscv::PLEN-3:0] pmpaddr_o,

	output logic [31:0] mcountinhibit_o
	output logic [ 31:0] mcountinhibit_o

	output logic en_ld_st_translation_o,
	output logic en_ld_st_translation_o,

Table builder for specification #1814

Table builder for specification #1814

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JeanRochCoulon commented Feb 7, 2024 •

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