Fix Verible and co

core/commit_stage.sv

@@ -33,7 +33,7 @@ module commit_stage
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic single_step_i,
     // The instruction we want to commit - ISSUE_STAGE
-    input  scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
+    input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     // Acknowledge that we are indeed committing - ISSUE_STAGE
     output logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_o,
     // Register file write address - ID_STAGE
@@ -55,7 +55,7 @@ module commit_stage
     // Data to read from CSR - CSR_REGFILE
     input riscv::xlen_t csr_rdata_i,
     // Exception or interrupt occurred in CSR stage (the same as commit) - CSR_REGFILE
-    input  exception_t csr_exception_i,
+    input exception_t csr_exception_i,
     // Write the fflags CSR - CSR_REGFILE
     output logic csr_write_fflags_o,
     // Commit the pending store - EX_STAGE

core/csr_regfile.sv

@@ -21,121 +21,121 @@ module csr_regfile
     parameter int unsigned           MHPMCounterNum = 6
 ) (
     // Subsystem Clock - SUBSYSTEM
-    input logic clk_i,
+    input  logic                                                           clk_i,
     // Asynchronous reset active low - SUBSYSTEM
-    input logic rst_ni,
+    input  logic                                                           rst_ni,
     // Timer threw a interrupt - SUBSYSTEM
-    input logic time_irq_i,
+    input  logic                                                           time_irq_i,
     // send a flush request out when a CSR with a side effect changes - CONTROLLER
-    output logic flush_o,
+    output logic                                                           flush_o,
     // halt requested - CONTROLLER
-    output logic halt_csr_o,
+    output logic                                                           halt_csr_o,
     // Instruction to be committed - ID_STAGE
-    input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
+    input  scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0]                  commit_instr_i,
     // Commit acknowledged a instruction -> increase instret CSR - COMMIT_STAGE
-    input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
+    input  logic              [CVA6Cfg.NrCommitPorts-1:0]                  commit_ack_i,
     // Address from which to start booting, mtvec is set to the same address - SUBSYSTEM
-    input logic[riscv::VLEN-1:0] boot_addr_i,
+    input  logic              [          riscv::VLEN-1:0]                  boot_addr_i,
     // Hart id in a multicore environment (reflected in a CSR) - SUBSYSTEM
-    input logic[riscv::XLEN-1:0] hart_id_i,
+    input  logic              [          riscv::XLEN-1:0]                  hart_id_i,
     // we are taking an exception
     // We've got an exception from the commit stage, take it - COMMIT_STAGE
-    input exception_t ex_i,
+    input  exception_t                                                     ex_i,
     // Operation to perform on the CSR file - COMMIT_STAGE
-    input fu_op csr_op_i,
+    input  fu_op                                                           csr_op_i,
     // Address of the register to read/write - EX_STAGE
-    input logic [11:0] csr_addr_i,
+    input  logic              [                     11:0]                  csr_addr_i,
     // Write data in - COMMIT_STAGE
-    input logic [riscv::XLEN-1:0] csr_wdata_i,
+    input  logic              [          riscv::XLEN-1:0]                  csr_wdata_i,
     // Read data out - COMMIT_STAGE
-    output logic [riscv::XLEN-1:0] csr_rdata_o,
+    output logic              [          riscv::XLEN-1:0]                  csr_rdata_o,
     // Mark the FP sate as dirty - COMMIT_STAGE
-    input logic dirty_fp_state_i,
+    input  logic                                                           dirty_fp_state_i,
     // Write fflags register e.g.: we are retiring a floating point instruction - COMMIT_STAGE
-    input  logic csr_write_fflags_i,
+    input  logic                                                           csr_write_fflags_i,
     // Mark the V state as dirty - ACC_DISPATCHER
-    input logic dirty_v_state_i,
+    input  logic                                                           dirty_v_state_i,
     // PC of instruction accessing the CSR - COMMIT_STAGE
-    input logic [riscv::VLEN-1:0] pc_i,
+    input  logic              [          riscv::VLEN-1:0]                  pc_i,
     // attempts to access a CSR without appropriate privilege - COMMIT_STAGE
-    output exception_t csr_exception_o,
+    output exception_t                                                     csr_exception_o,
     // Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly - FRONTEND
-    output logic [riscv::VLEN-1:0] epc_o,
+    output logic              [          riscv::VLEN-1:0]                  epc_o,
     // Return from exception, set the PC of epc_o - FRONTEND
-    output logic eret_o,
+    output logic                                                           eret_o,
     // Output base of exception vector, correct CSR is output (mtvec, stvec) - FRONTEND
-    output logic [riscv::VLEN-1:0] trap_vector_base_o,
+    output logic              [          riscv::VLEN-1:0]                  trap_vector_base_o,
     // Current privilege level the CPU is in - EX_STAGE
-    output riscv::priv_lvl_t priv_lvl_o,
+    output riscv::priv_lvl_t                                               priv_lvl_o,
     // Imprecise FP exception from the accelerator (fcsr.fflags format) - ACC_DISPATCHER
-    input  logic [4:0] acc_fflags_ex_i,
+    input  logic              [                      4:0]                  acc_fflags_ex_i,
     // An FP exception from the accelerator occurred - ACC_DISPATCHER
-    input logic acc_fflags_ex_valid_i,
+    input  logic                                                           acc_fflags_ex_valid_i,
     // Floating point extension status - ID_STAGE
-    output riscv::xs_t fs_o,
+    output riscv::xs_t                                                     fs_o,
     // Floating-Point Accured Exceptions - COMMIT_STAGE
-    output logic [4:0] fflags_o,
+    output logic              [                      4:0]                  fflags_o,
     // Floating-Point Dynamic Rounding Mode - EX_STAGE
-    output logic [2:0] frm_o,
+    output logic              [                      2:0]                  frm_o,
     // Floating-Point Precision Control - EX_STAGE
-    output logic [6:0] fprec_o,
+    output logic              [                      6:0]                  fprec_o,
     // Vector extension status - ID_STAGE
-    output riscv::xs_t vs_o,
+    output riscv::xs_t                                                     vs_o,
     // interrupt management to id stage - ID_STAGE
-    output irq_ctrl_t irq_ctrl_o,
+    output irq_ctrl_t                                                      irq_ctrl_o,
     // enable VA translation - EX_STAGE
-    output logic en_translation_o,
+    output logic                                                           en_translation_o,
     // enable VA translation for load and stores - EX_STAGE
-    output logic en_ld_st_translation_o,
+    output logic                                                           en_ld_st_translation_o,
     // Privilege level at which load and stores should happen - EX_STAGE
-    output riscv::priv_lvl_t      ld_st_priv_lvl_o,
+    output riscv::priv_lvl_t                                               ld_st_priv_lvl_o,
     // TO_BE_COMPLETED - EX_STAGE
-    output logic sum_o,
+    output logic                                                           sum_o,
     // TO_BE_COMPLETED - EX_STAGE
-    output logic mxr_o,
+    output logic                                                           mxr_o,
     // TO_BE_COMPLETED - EX_STAGE
-    output logic [riscv::PPNW-1:0] satp_ppn_o,
+    output logic              [          riscv::PPNW-1:0]                  satp_ppn_o,
     // TO_BE_COMPLETED - EX_STAGE
-    output logic [AsidWidth-1:0] asid_o,
+    output logic              [            AsidWidth-1:0]                  asid_o,
     // external interrupt in - SUBSYSTEM
-    input logic [1:0] irq_i,
+    input  logic              [                      1:0]                  irq_i,
     // inter processor interrupt -> connected to machine mode sw - SUBSYSTEM
-    input logic ipi_i,
+    input  logic                                                           ipi_i,
     // debug request in - ID_STAGE
-    input logic debug_req_i,
+    input  logic                                                           debug_req_i,
     // TO_BE_COMPLETED - FRONTEND
-    output logic set_debug_pc_o,
+    output logic                                                           set_debug_pc_o,
     // trap virtual memory - ID_STAGE
-    output logic tvm_o,
+    output logic                                                           tvm_o,
     // timeout wait - ID_STAGE
-    output logic tw_o,
+    output logic                                                           tw_o,
     // trap sret - ID_STAGE
-    output logic tsr_o,
+    output logic                                                           tsr_o,
     // we are in debug mode -> that will change some decoding - EX_STAGE
-    output logic debug_mode_o,
+    output logic                                                           debug_mode_o,
     // we are in single-step mode - COMMIT_STAGE
-    output logic single_step_o,
+    output logic                                                           single_step_o,
     // L1 ICache Enable - CACHE
-    output logic icache_en_o,
+    output logic                                                           icache_en_o,
     // L1 DCache Enable - CACHE
-    output logic dcache_en_o,
+    output logic                                                           dcache_en_o,
     // Accelerator memory consistent mode - ACC_DISPATCHER
-    output logic acc_cons_en_o,
+    output logic                                                           acc_cons_en_o,
     // Performance Counter
     // read/write address to performance counter module - PERF_COUNTERS
-    output logic [11:0] perf_addr_o,
+    output logic              [                     11:0]                  perf_addr_o,
     // write data to performance counter module - PERF_COUNTERS
-    output logic [riscv::XLEN-1:0] perf_data_o,
+    output logic              [          riscv::XLEN-1:0]                  perf_data_o,
     // read data from performance counter module - PERF_COUNTERS
-    input logic [riscv::XLEN-1:0] perf_data_i,
+    input  logic              [          riscv::XLEN-1:0]                  perf_data_i,
     // TO_BE_COMPLETED - PERF_COUNTERS
-    output logic perf_we_o,
+    output logic                                                           perf_we_o,
     // PMP configuration containing pmpcfg for max 16 PMPs - ACC_DISPATCHER
-    output riscv::pmpcfg_t [15:0] pmpcfg_o,
+    output riscv::pmpcfg_t    [                     15:0]                  pmpcfg_o,
     // PMP addresses - ACC_DISPATCHER
-    output logic [15:0][riscv::PLEN-3:0] pmpaddr_o,
+    output logic              [                     15:0][riscv::PLEN-3:0] pmpaddr_o,
     // TO_BE_COMPLETED - PERF_COUNTERS
-    output logic [31:0] mcountinhibit_o
+    output logic              [                     31:0]                  mcountinhibit_o
 );
   // internal signal to keep track of access exceptions
   logic read_access_exception, update_access_exception, privilege_violation;

core/ex_stage.sv

@@ -159,7 +159,7 @@ module ex_stage
     // TO_BE_COMPLETED - CSR_REGFILE
     input logic [ASID_WIDTH-1:0] asid_i,
     // icache translation response - CACHE
-    input  icache_arsp_t icache_areq_i,
+    input icache_arsp_t icache_areq_i,
     // icache translation request - CACHE
     output icache_areq_t icache_areq_o,
     // TO_BE_COMPLETED - CACHE

core/include/cv32a65x_config_pkg.sv

@@ -92,7 +92,6 @@ package cva6_config_pkg;
       XFVec: bit'(CVA6ConfigFVecEn),
       CvxifEn: bit'(CVA6ConfigCvxifEn),
       ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
-      // Extended
       RVF: bit'(0),
       RVD: bit'(0),
       FpPresent: bit'(0),
@@ -119,15 +118,12 @@ package cva6_config_pkg;
       PMPAddrRstVal: {16{64'h0}},
       PMPEntryReadOnly: 16'd0,
       NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
-      // idempotent region
       NrNonIdempotentRules: unsigned'(2),
       NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
       NonIdempotentLength: 1024'({64'b0, 64'b0}),
       NrExecuteRegionRules: unsigned'(3),
-      //                      DRAM,          Boot ROM,   Debug Module
       ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
       ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
-      // cached region
       NrCachedRegionRules: unsigned'(1),
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),

core/issue_stage.sv

@@ -108,7 +108,7 @@ module issue_stage
     // TO_BE_COMPLETED - EX_STAGE
     input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
     // TO_BE_COMPLETED - COMMIT_STAGE
-    output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] COMMIT_STAGE,
+    output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
     // Issue stall - PERF_COUNTERS

docs/04_cv32a65x_design/source/port_bht.rst

@@ -45,7 +45,7 @@
    * - ``vpc_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Virtual PC
 
    * - ``bht_update_i``
@@ -57,5 +57,5 @@
    * - ``bht_prediction_o``
      - out
      - FRONTEND
-     - ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
      - Prediction from bht

docs/04_cv32a65x_design/source/port_btb.rst

@@ -45,7 +45,7 @@
    * - ``vpc_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Virtual PC
 
    * - ``btb_update_i``
@@ -57,5 +57,5 @@
    * - ``btb_prediction_o``
      - out
      - FRONTEND
-     - ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
      - BTB Prediction

docs/04_cv32a65x_design/source/port_commit_stage.rst

@@ -60,34 +60,40 @@
      - logic
      - TO_BE_COMPLETED
 
+   * - ``commit_instr_i``
+     - in
+     - ISSUE_STAGE
+     - scoreboard_entry_t[CVA6Cfg.NrCommitPorts-1:0]
+     - The instruction we want to commit
+
    * - ``commit_ack_o``
      - out
      - ISSUE_STAGE
-     - logic [CVA6Cfg.NrCommitPorts-1:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
      - Acknowledge that we are indeed committing
 
    * - ``waddr_o``
      - out
      - ID_STAGE
-     - logic [CVA6Cfg.NrCommitPorts-1:0][4:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0][4:0]
      - Register file write address
 
    * - ``wdata_o``
      - out
      - ID_STAGE
-     - logic [CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
      - Register file write data
 
    * - ``we_gpr_o``
      - out
      - ID_STAGE
-     - logic [CVA6Cfg.NrCommitPorts-1:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
      - Register file write enable
 
    * - ``we_fpr_o``
      - out
      - ID_STAGE
-     - logic [CVA6Cfg.NrCommitPorts-1:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
      - Floating point register enable
 
    * - ``amo_resp_i``
@@ -99,7 +105,7 @@
    * - ``pc_o``
      - out
      - FRONTEND_CSR
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - TO_BE_COMPLETED
 
    * - ``csr_op_o``
@@ -123,7 +129,7 @@
    * - ``csr_exception_i``
      - in
      - CSR_REGFILE
-     -  exception_t
+     - exception_t
      - Exception or interrupt occurred in CSR stage (the same as commit)
 
    * - ``csr_write_fflags_o``
@@ -147,7 +153,7 @@
    * - ``commit_tran_id_o``
      - out
      - ID_STAGE
-     - logic [TRANS_ID_BITS-1:0]
+     - logic[TRANS_ID_BITS-1:0]
      - Transaction id of first commit port
 
    * - ``amo_valid_commit_o``