Fix Verible & co

core/include/cv32a65x_config_pkg.sv

@@ -92,7 +92,6 @@ package cva6_config_pkg;
       XFVec: bit'(CVA6ConfigFVecEn),
       CvxifEn: bit'(CVA6ConfigCvxifEn),
       ZiCondExtEn: bit'(CVA6ConfigZiCondExtEn),
-      // Extended
       RVF: bit'(0),
       RVD: bit'(0),
       FpPresent: bit'(0),
@@ -119,15 +118,12 @@ package cva6_config_pkg;
       PMPAddrRstVal: {16{64'h0}},
       PMPEntryReadOnly: 16'd0,
       NOCType: config_pkg::NOC_TYPE_AXI4_ATOP,
-      // idempotent region
       NrNonIdempotentRules: unsigned'(2),
       NonIdempotentAddrBase: 1024'({64'b0, 64'b0}),
       NonIdempotentLength: 1024'({64'b0, 64'b0}),
       NrExecuteRegionRules: unsigned'(3),
-      //                      DRAM,          Boot ROM,   Debug Module
       ExecuteRegionAddrBase: 1024'({64'h8000_0000, 64'h1_0000, 64'h0}),
       ExecuteRegionLength: 1024'({64'h40000000, 64'h10000, 64'h1000}),
-      // cached region
       NrCachedRegionRules: unsigned'(1),
       CachedRegionAddrBase: 1024'({64'h8000_0000}),
       CachedRegionLength: 1024'({64'h40000000}),

core/issue_stage.sv

@@ -108,7 +108,7 @@ module issue_stage
     // TO_BE_COMPLETED - EX_STAGE
     input logic [CVA6Cfg.NrCommitPorts-1:0] we_fpr_i,
     // TO_BE_COMPLETED - COMMIT_STAGE
-    output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] COMMIT_STAGE,
+    output scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_o,
     // TO_BE_COMPLETED - COMMIT_STAGE
     input logic [CVA6Cfg.NrCommitPorts-1:0] commit_ack_i,
     // Issue stall - PERF_COUNTERS

docs/04_cv32a65x_design/source/port_bht.rst

@@ -45,7 +45,7 @@
    * - ``vpc_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Virtual PC
 
    * - ``bht_update_i``
@@ -57,5 +57,5 @@
    * - ``bht_prediction_o``
      - out
      - FRONTEND
-     - ariane_pkg::bht_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
      - Prediction from bht

docs/04_cv32a65x_design/source/port_btb.rst

@@ -45,7 +45,7 @@
    * - ``vpc_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Virtual PC
 
    * - ``btb_update_i``
@@ -57,5 +57,5 @@
    * - ``btb_prediction_o``
      - out
      - FRONTEND
-     - ariane_pkg::btb_prediction_t [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
      - BTB Prediction

docs/04_cv32a65x_design/source/port_cva6.rst

@@ -33,19 +33,19 @@
    * - ``boot_addr_i``
      - in
      - SUBSYSTEM
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Reset boot address
 
    * - ``hart_id_i``
      - in
      - SUBSYSTEM
-     - logic [riscv::XLEN-1:0]
+     - logic[riscv::XLEN-1:0]
      - Hard ID reflected as CSR
 
    * - ``irq_i``
      - in
      - SUBSYSTEM
-     - logic [1:0]
+     - logic[1:0]
      - Level sensitive (async) interrupts
 
    * - ``ipi_i``

docs/04_cv32a65x_design/source/port_frontend.rst

@@ -57,7 +57,7 @@
    * - ``boot_addr_i``
      - in
      - SUBSYSTEM
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Next PC when reset
 
    * - ``resolved_branch_i``
@@ -75,13 +75,13 @@
    * - ``pc_commit_i``
      - in
      - COMMIT
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Next PC when flushing pipeline
 
    * - ``epc_i``
      - in
      - CSR
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Next PC when returning from exception
 
    * - ``eret_i``
@@ -93,7 +93,7 @@
    * - ``trap_vector_base_i``
      - in
      - CSR
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Next PC when jumping into exception
 
    * - ``ex_valid_i``

docs/04_cv32a65x_design/source/port_id_stage.rst

@@ -69,7 +69,7 @@
    * - ``orig_instr_o``
      - out
      - ISSUE
-     - logic [31:0]
+     - logic[31:0]
      - instruction value
 
    * - ``issue_entry_valid_o``
@@ -111,7 +111,7 @@
    * - ``frm_i``
      - in
      - CSR
-     - logic [2:0]
+     - logic[2:0]
      - Report floating point dynamic rounding mode
 
    * - ``vs_i``
@@ -123,7 +123,7 @@
    * - ``irq_i``
      - in
      - SUBSYSTEM
-     - logic [1:0]
+     - logic[1:0]
      - Level sensitive (async) interrupts
 
    * - ``irq_ctrl_i``

docs/04_cv32a65x_design/source/port_instr_queue.rst

@@ -39,19 +39,19 @@
    * - ``instr_i``
      - in
      - instr_realign
-     - logic [ariane_pkg::INSTR_PER_FETCH-1:0][31:0]
+     - logic[ariane_pkg::INSTR_PER_FETCH-1:0][31:0]
      - Instruction
 
    * - ``addr_i``
      - in
      - instr_realign
-     - logic [ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
+     - logic[ariane_pkg::INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
      - Instruction address
 
    * - ``valid_i``
      - in
      - instr_realign
-     - logic [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - logic[ariane_pkg::INSTR_PER_FETCH-1:0]
      - Instruction is valid
 
    * - ``ready_o``
@@ -63,7 +63,7 @@
    * - ``consumed_o``
      - out
      - FRONTEND
-     - logic [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - logic[ariane_pkg::INSTR_PER_FETCH-1:0]
      - Indicates instructions consummed, or popped by ID_STAGE
 
    * - ``exception_i``
@@ -75,19 +75,19 @@
    * - ``exception_addr_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Exception address
 
    * - ``predict_address_i``
      - in
      - FRONTEND
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Branch predict
 
    * - ``cf_type_i``
      - in
      - FRONTEND
-     - ariane_pkg::cf_t [ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::cf_t[ariane_pkg::INSTR_PER_FETCH-1:0]
      - Instruction predict address
 
    * - ``replay_o``
@@ -99,7 +99,7 @@
    * - ``replay_addr_o``
      - out
      - FRONTEND
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Address at which to replay the fetch
 
    * - ``fetch_entry_o``

docs/04_cv32a65x_design/source/port_instr_realign.rst

@@ -51,29 +51,29 @@
    * - ``address_i``
      - in
      - CACHE
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - 32-bit block address
 
    * - ``data_i``
      - in
      - CACHE
-     - logic [FETCH_WIDTH-1:0]
+     - logic[FETCH_WIDTH-1:0]
      - 32-bit block
 
    * - ``valid_o``
      - out
      - FRONTEND
-     - logic [INSTR_PER_FETCH-1:0]
+     - logic[INSTR_PER_FETCH-1:0]
      - instruction is valid
 
    * - ``addr_o``
      - out
      - FRONTEND
-     - logic [INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
+     - logic[INSTR_PER_FETCH-1:0][riscv::VLEN-1:0]
      - Instruction address
 
    * - ``instr_o``
      - out
      - none
-     - logic [INSTR_PER_FETCH-1:0][31:0]
+     - logic[INSTR_PER_FETCH-1:0][31:0]
      - none

docs/04_cv32a65x_design/source/port_instr_scan.rst

@@ -21,7 +21,7 @@
    * - ``instr_i``
      - in
      - instr_realign
-     - logic [31:0]
+     - logic[31:0]
      - Instruction to be predecoded
 
    * - ``rvi_return_o``
@@ -57,7 +57,7 @@
    * - ``rvi_imm_o``
      - out
      - FRONTEND
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Instruction immediat
 
    * - ``rvc_branch_o``
@@ -99,5 +99,5 @@
    * - ``rvc_imm_o``
      - out
      - FRONTEND
-     - logic [riscv::VLEN-1:0]
+     - logic[riscv::VLEN-1:0]
      - Instruction compressed immediat