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Issues: chipsalliance/treadle

15 Open 44 Closed
15 Open 44 Closed
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Issues list

Out of heap memory when generating VCD waveform
#441 opened Aug 1, 2023 by liuxd17thu
More than two clocks at top level of dut issues warning bug Something isn't working
#358 opened Sep 10, 2021 by chick
@chick
1
Use logging instead of println cleanup Fixing up stale code
#353 opened Aug 24, 2021 by chick
@chick
Make it possible to create a TreadleTester without running firrtl optimizations
#352 opened Aug 23, 2021 by ekiwi
@chick
3
Add support for the PresetRegAnnotation
#329 opened May 20, 2021 by ekiwi
2
Add support for SAIF dump
#306 opened Mar 5, 2021 by hansemandse
3
Building a BlackBox from firrtl source.
#293 opened Jan 5, 2021 by mminutoli
Provide a convenience method to launch treadle REPL on a chisel design
#242 opened Aug 12, 2020 by chick
Is it possible to access signals in clockChange?
#219 opened Jul 9, 2020 by davidmlw
2
Build Scala black boxes to match rocket-chip verilog black boxes enhancement New feature or request
#148 opened Nov 5, 2019 by chick
@chick
2
Incorrect BlackBoxes input values changes
#116 opened Aug 1, 2019 by johnsbrew
9
Add support for FST output
#101 opened May 20, 2019 by ekiwi
5
[RFC] Allow users to create Scala versions of any firrtl module enhancement New feature or request
#68 opened Dec 4, 2018 by chick
@chick
1
Unresovled BlackBox issues enhancement New feature or request
#67 opened Nov 29, 2018 by chick
@chick
Add Support for [Sparse] Mems larger than 2^31 - 1 (ie. BigInt address)
#51 opened Jul 17, 2018 by jackkoenig
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