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This repository has been archived by the owner on Aug 21, 2024. It is now read-only.
I am in the process of adding support for memories with BigInt addresses to Chisel and FIRRTL. In practice, these will just be sparse memories for simulation purposes since it's not practice to create such large SRAMs. However, it can be useful to model massive virtual memory spaces even if they're sparsely populated in simulation.
Initially, the API change can be supported by just casting the address back to an Int and erroring if it is too large. Ultimately I do think that sparse memory support can be useful though!
I am in the process of adding support for memories with BigInt addresses to Chisel and FIRRTL. In practice, these will just be sparse memories for simulation purposes since it's not practice to create such large SRAMs. However, it can be useful to model massive virtual memory spaces even if they're sparsely populated in simulation.
Initially, the API change can be supported by just casting the address back to an Int and erroring if it is too large. Ultimately I do think that sparse memory support can be useful though!
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