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More than two clocks at top level of dut issues warning #358

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chick opened this issue Sep 10, 2021 · 1 comment
Open

More than two clocks at top level of dut issues warning #358

chick opened this issue Sep 10, 2021 · 1 comment
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chick commented Sep 10, 2021

In TreadleTester.scala:88
Maybe this should be >= 2 instead of >2
@chick chick added the bug Something isn't working label Sep 10, 2021
@chick chick self-assigned this Sep 10, 2021
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ekiwi commented Sep 17, 2021

I think the problem is the implementation of findTopLevelClocks. The function should ideally only consider input ports. Currently it considers a lot of derived clock signals to be independent clocks.

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