tools/riscv-dv: add a separate testlist.yaml #176
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Links to coverage and verification reports for this PR (#176) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#176) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#176) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
This commit adds a separate testlist suite, with only one specified
PMP test for now.
The PMP test can be selected by setting the `RISCV_DV_TEST` variable:
RISCV_DV_TEST=riscv_pmp_test RISCV_DV_SIM=<sim> make generate run
Signed-off-by: Filip Kokosinski <[email protected]>
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Links to coverage and verification reports for this PR (#176) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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Links to coverage and verification reports for this PR (#176) are available at https://chipsalliance.github.io/Cores-VeeR-EL2/ |
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LGTM |
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This PR adds a separate testlist suite, with only one specified PMP test for now. The PMP test can be selected by setting the
RISCV_DV_TESTvariable: