Merge pull request #176 from antmicro/fkokosinski/59782-riscv-dv-exte…

…nsion tools/riscv-dv: add a separate testlist.yaml
chipsalliance · Jun 7, 2024 · 455648f · 455648f
2 parents a8a87f3 + 2ad22bb
commit 455648f
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Showing 6 changed files with 685 additions and 3 deletions.
diff --git a/.github/scripts/riscv_dv_parse_testlist.py b/.github/scripts/riscv_dv_parse_testlist.py
@@ -1,4 +1,5 @@
 import sys
+import os
 from json import dumps
 from yaml import load, Loader
 from typing import Generator
@@ -19,8 +20,15 @@ def parse_yaml(path: str) -> Generator[str, None, None]:
 
 if __name__ == "__main__":
     if len(sys.argv) == 2:
-        testlist = parse_yaml(
-            RISCV_DV_HOME + f'target/{sys.argv[1]}/testlist.yaml')
+        testlist = RISCV_DV_HOME + f'target/{sys.argv[1]}/testlist.yaml'
+
+        # check if testlist.yaml is provided by RISCV-DV; if not - it's a
+        # custom testlist file not provided by RISCV-DV by default; treat the
+        # script argument as full a path
+        if not os.path.isdir(testlist):
+            testlist = sys.argv[1]
+
+        testlist = parse_yaml(testlist)
     else:
         testlist = parse_yaml(RISCV_DV_HOME + 'yaml/base_testlist.yaml')
     testlist = list(testlist)

diff --git a/.github/workflows/test-riscv-dv.yml b/.github/workflows/test-riscv-dv.yml
@@ -119,7 +119,7 @@ jobs:
       - id: test-types
         run: |
           python3 -m pip install pyyaml
-          echo "tests=$(python3 .github/scripts/riscv_dv_parse_testlist.py rv32imc)" | tee -a $GITHUB_OUTPUT
+          echo "tests=$(python3 .github/scripts/riscv_dv_parse_testlist.py tools/riscv-dv/testlist.yaml)" | tee -a $GITHUB_OUTPUT
           echo "include-generate=$(python3 .github/scripts/riscv_dv_matrix_include.py generate)" | tee -a $GITHUB_OUTPUT
           echo "include-run=$(python3 .github/scripts/riscv_dv_matrix_include.py run)" | tee -a $GITHUB_OUTPUT
       - id: hash

diff --git a/tools/riscv-dv/Makefile b/tools/riscv-dv/Makefile
@@ -48,6 +48,8 @@ RISCV_DV_ARGS = \
     --iterations $(RISCV_DV_ITER) \
     --batch_size $(RISCV_DV_BATCH) \
     --isa rv32imc --mabi ilp32 \
+    --custom_target $(PWD) \
+    --testlist $(PWD)/testlist.yaml \
     -v -o $(TEST_DIR)
 
 MAKEFILE  = $(abspath $(MAKEFILE_LIST))
@@ -141,7 +143,13 @@ $(WORK_DIR)/coverage.dat:
 		touch $@ ; \
 	fi
 
+%.sv: %.py
+	./$< $(RISCV_DV_PATH) $(RV_ROOT) > $@
+
 generate:
+	# Generate *.sv configuration
+	#$(MAKE) -f $(MAKEFILE) riscv_core_setting.sv
+
 	# Run RISC-V DV code generation
 	$(MAKE) -f $(MAKEFILE) $(TEST_DIR)/generate.log