[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:22:-`include "el2_param.vh" design/el2_mem.sv:23:- ) design/el2_mem.sv:24:-( design/el2_mem.sv:25:- input logic clk, design/el2_mem.sv:26:- input logic rst_l, design/el2_mem.sv:27:- input logic dccm_clk_override, design/el2_mem.sv:28:- input logic icm_clk_override, design/el2_mem.sv:29:- input logic dec_tlu_core_ecc_disable, design/el2_mem.sv:30:- design/el2_mem.sv:31:- //DCCM ports design/el2_mem.sv:32:- input logic dccm_wren, design/el2_mem.sv:33:- input logic dccm_rden, design/el2_mem.sv:34:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_lo, design/el2_mem.sv:35:- input logic [pt.DCCM_BITS-1:0] dccm_wr_addr_hi, design/el2_mem.sv:36:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_lo, design/el2_mem.sv:37:- input logic [pt.DCCM_BITS-1:0] dccm_rd_addr_hi, design/el2_mem.sv:38:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, design/el2_mem.sv:39:- input logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, design/el2_mem.sv:40:- design/el2_mem.sv:41:- design/el2_mem.sv:42:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, design/el2_mem.sv:43:- output logic [pt.DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, design/el2_mem.sv:44:- design/el2_mem.sv:45:- //ICCM ports design/el2_mem.sv:46:- input logic [pt.ICCM_BITS-1:1] iccm_rw_addr, design/el2_mem.sv:47:- input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle design/el2_mem.sv:48:- input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle design/el2_mem.sv:49:- input logic iccm_wren, design/el2_mem.sv:50:- input logic iccm_rden, design/el2_mem.sv:51:- input logic [2:0] iccm_wr_size, design/el2_mem.sv:52:- input logic [77:0] iccm_wr_data, design/el2_mem.sv:53:- design/el2_mem.sv:54:- output logic [63:0] iccm_rd_data, design/el2_mem.sv:55:- output logic [77:0] iccm_rd_data_ecc, design/el2_mem.sv:56:- design/el2_mem.sv:57:- // Icache and Itag Ports design/el2_mem.sv:58:- design/el2_mem.sv:59:- input logic [31:1] ic_rw_addr, design/el2_mem.sv:60:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, design/el2_mem.sv:61:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en, design/el2_mem.sv:62:- input logic ic_rd_en, design/el2_mem.sv:63:- input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. design/el2_mem.sv:64:- input logic ic_sel_premux_data, // Premux data sel design/el2_mem.sv:65:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_mem.sv:66:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_mem.sv:67:- design/el2_mem.sv:68:- input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC design/el2_mem.sv:69:- input logic [70:0] ic_debug_wr_data, // Debug wr cache. design/el2_mem.sv:70:- output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/el2_mem.sv:71:- input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. design/el2_mem.sv:72:- input logic ic_debug_rd_en, // Icache debug rd design/el2_mem.sv:73:- input logic ic_debug_wr_en, // Icache debug wr design/el2_mem.sv:74:- input logic ic_debug_tag_array, // Debug tag array design/el2_mem.sv:75:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. design/el2_mem.sv:76:- design/el2_mem.sv:77:- output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/e

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:96:- logic active_clk; design/el2_mem.sv:97:- rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* ); design/el2_mem.sv:98:- design/el2_mem.sv:99:- el2_mem_if mem_export_local (); design/el2_mem.sv:100:- design/el2_mem.sv:101:- assign mem_export .clk = clk; design/el2_mem.sv:102:- assign icache_export .clk = clk; design/el2_mem.sv:103:- assign mem_export_local.clk = clk; design/el2_mem.sv:104:- design/el2_mem.sv:105:- assign mem_export .iccm_clken = mem_export_local.iccm_clken; design/el2_mem.sv:106:- assign mem_export .iccm_wren_bank = mem_export_local.iccm_wren_bank; design/el2_mem.sv:107:- assign mem_export .iccm_addr_bank = mem_export_local.iccm_addr_bank; design/el2_mem.sv:108:- assign mem_export .iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data; design/el2_mem.sv:109:- assign mem_export .iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc; design/el2_mem.sv:110:- assign mem_export_local.iccm_bank_dout = mem_export. iccm_bank_dout; design/el2_mem.sv:111:- assign mem_export_local.iccm_bank_ecc = mem_export. iccm_bank_ecc; design/el2_mem.sv:112:- design/el2_mem.sv:113:- assign mem_export .dccm_clken = mem_export_local.dccm_clken; design/el2_mem.sv:114:- assign mem_export .dccm_wren_bank = mem_export_local.dccm_wren_bank; design/el2_mem.sv:115:- assign mem_export .dccm_addr_bank = mem_export_local.dccm_addr_bank; design/el2_mem.sv:116:- assign mem_export .dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank; design/el2_mem.sv:117:- assign mem_export .dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank; design/el2_mem.sv:118:- assign mem_export_local.dccm_bank_dout = mem_export .dccm_bank_dout; design/el2_mem.sv:119:- assign mem_export_local.dccm_bank_ecc = mem_export .dccm_bank_ecc; design/el2_mem.sv:120:- design/el2_mem.sv:121:- // icache data design/el2_mem.sv:122:- assign icache_export .ic_b_sb_wren = mem_export_local.ic_b_sb_wren; design/el2_mem.sv:123:- assign icache_export .ic_b_sb_bit_en_vec = mem_export_local.ic_b_sb_bit_en_vec; design/el2_mem.sv:124:- assign icache_export .ic_sb_wr_data = mem_export_local.ic_sb_wr_data; design/el2_mem.sv:125:- assign icache_export .ic_rw_addr_bank_q = mem_export_local.ic_rw_addr_bank_q; design/el2_mem.sv:126:- assign icache_export .ic_bank_way_clken_final = mem_export_local.ic_bank_way_clken_final; design/el2_mem.sv:127:- assign icache_export .ic_bank_way_clken_final_up = mem_export_local.ic_bank_way_clken_final_up; design/el2_mem.sv:128:- assign mem_export_local.wb_packeddout_pre = icache_export .wb_packeddout_pre; design/el2_mem.sv:129:- assign mem_export_local.wb_dout_pre_up = icache_export .wb_dout_pre_up; design/el2_mem.sv:130:- design/el2_mem.sv:131:- // icache tag design/el2_mem.sv:132:- assign icache_export .ic_tag_clken_final = mem_export_local.ic_tag_clken_final; design/el2_mem.sv:133:- assign icache_export .ic_tag_wren_q = mem_export_local.ic_tag_wren_q; design/el2_mem.sv:134:- assign icache_export .ic_tag_wren_biten_vec = mem_export_local.ic_tag_wren_biten_vec; design/el2_mem.sv:135:- assign icache_export .ic_tag_wr_data = mem_export_local.ic_tag_wr_data; design/el2_mem.sv:136:- assign icache_export .ic_rw_addr_q = mem_export_local.ic_rw_addr_q; design/el2_mem.sv:137:- assign mem_export_local.ic_tag_data_raw_packed_pre = icache_export .ic_tag_data_raw_packed_pre; design/el2_mem.sv:138:- assign mem_export_local.ic_tag_data_raw_pre = icache_export .ic_tag_data_raw_pre; design/el2_mem.sv:139:- design/el2_mem.sv:140:- // DCCM Instantiation design/el2_mem.sv:141:- if (pt.DCCM_ENABLE == 1) begin: Gen_dccm_enable design/el2_mem.sv:142:- el2_lsu_dccm_mem #(.pt(pt)) dccm ( design/el2_mem.sv:143:-

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_mem.sv:157:- ); design/el2_mem.sv:158:-end design/el2_mem.sv:159:-else begin design/el2_mem.sv:160:- assign ic_rd_hit[pt.ICACHE_NUM_WAYS-1:0] = '0; design/el2_mem.sv:161:- assign ic_tag_perr = '0 ; design/el2_mem.sv:162:- assign ic_rd_data = '0 ; design/el2_mem.sv:163:- assign ictag_debug_rd_data = '0 ; design/el2_mem.sv:164:- assign ic_debug_rd_data = '0 ; design/el2_mem.sv:165:- assign ic_eccerr = '0; design/el2_mem.sv:166:-end // else: !if( pt.ICACHE_ENABLE ) design/el2_mem.sv:167:- design/el2_mem.sv:168:- design/el2_mem.sv:169:- design/el2_mem.sv:170:-if (pt.ICCM_ENABLE) begin : iccm design/el2_mem.sv:171:- el2_ifu_iccm_mem #(.pt(pt)) iccm (.*, design/el2_mem.sv:172:- .clk_override(icm_clk_override), design/el2_mem.sv:173:- .iccm_rw_addr(iccm_rw_addr[pt.ICCM_BITS-1:1]), design/el2_mem.sv:174:- .iccm_rd_data(iccm_rd_data[63:0]), design/el2_mem.sv:175:- .iccm_mem_export(mem_export_local.veer_iccm) design/el2_mem.sv:176:- ); design/el2_mem.sv:177:-end design/el2_mem.sv:178:-else begin design/el2_mem.sv:179:- assign iccm_rd_data = '0 ; design/el2_mem.sv:180:- assign iccm_rd_data_ecc = '0 ; design/el2_mem.sv:181:-end design/el2_mem.sv:100:+ ); design/el2_mem.sv:101:+ design/el2_mem.sv:102:+ el2_mem_if mem_export_local (); design/el2_mem.sv:103:+ design/el2_mem.sv:104:+ assign mem_export.clk = clk; design/el2_mem.sv:105:+ assign icache_export.clk = clk; design/el2_mem.sv:106:+ assign mem_export_local.clk = clk; design/el2_mem.sv:107:+ design/el2_mem.sv:108:+ assign mem_export.iccm_clken = mem_export_local.iccm_clken; design/el2_mem.sv:109:+ assign mem_export.iccm_wren_bank = mem_export_local.iccm_wren_bank; design/el2_mem.sv:110:+ assign mem_export.iccm_addr_bank = mem_export_local.iccm_addr_bank; design/el2_mem.sv:111:+ assign mem_export.iccm_bank_wr_data = mem_export_local.iccm_bank_wr_data; design/el2_mem.sv:112:+ assign mem_export.iccm_bank_wr_ecc = mem_export_local.iccm_bank_wr_ecc; design/el2_mem.sv:113:+ assign mem_export_local.iccm_bank_dout = mem_export.iccm_bank_dout; design/el2_mem.sv:114:+ assign mem_export_local.iccm_bank_ecc = mem_export.iccm_bank_ecc; design/el2_mem.sv:115:+ design/el2_mem.sv:116:+ assign mem_export.dccm_clken = mem_export_local.dccm_clken; design/el2_mem.sv:117:+ assign mem_export.dccm_wren_bank = mem_export_local.dccm_wren_bank; design/el2_mem.sv:118:+ assign mem_export.dccm_addr_bank = mem_export_local.dccm_addr_bank; design/el2_mem.sv:119:+ assign mem_export.dccm_wr_data_bank = mem_export_local.dccm_wr_data_bank; design/el2_mem.sv:120:+ assign mem_export.dccm_wr_ecc_bank = mem_export_local.dccm_wr_ecc_bank; design/el2_mem.sv:121:+ assign mem_export_local.dccm_bank_dout = mem_export.dccm_bank_dout; design/el2_mem.sv:122:+ assign mem_export_local.dccm_bank_ecc = mem_export.dccm_bank_ecc; design/el2_mem.sv:123:+ design/el2_mem.sv:124:+ // icache data design/el2_mem.sv:125:+ assign icache_export.ic_b_sb_wren = mem_export_local.ic_b_sb_wren; design/el2_mem.sv:126:+ assign icache_export.ic_b_sb_bit_en_vec = mem_export_local.ic_b_sb_bit_en_vec; design/el2_mem.sv:127:+ assign icache_export.ic_sb_wr_data = mem_export_local.ic_sb_wr_data; design/el2_mem.sv:128:+ assign icache_export.ic_rw_addr_bank_q = mem_export_local.ic_rw_addr_bank_q; design/el2_mem.sv:129:+ assign icache_export.ic_bank_way_clken_final = mem_export_local.ic_bank_way_clken_final; design/el2_mem.sv:130:+ assign icache_export.ic_bank_way_clken_final_up = mem_export_local.ic_bank_way_clken_final_up; design/el2_mem.sv:131:+ assign mem_

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:378:- // clk ratio signals design/el2_veer_wrapper.sv:379:- input logic lsu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:380:- input logic ifu_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:381:- input logic dbg_bus_clk_en, // Clock ratio b/w cpu core clk & AHB master interface design/el2_veer_wrapper.sv:382:- input logic dma_bus_clk_en, // Clock ratio b/w cpu core clk & AHB slave interface design/el2_veer_wrapper.sv:383:- design/el2_veer_wrapper.sv:384:- // ICCM/DCCM ECC status design/el2_veer_wrapper.sv:385:- output logic iccm_ecc_single_error, design/el2_veer_wrapper.sv:386:- output logic iccm_ecc_double_error, design/el2_veer_wrapper.sv:387:- output logic dccm_ecc_single_error, design/el2_veer_wrapper.sv:388:- output logic dccm_ecc_double_error, design/el2_veer_wrapper.sv:389:- design/el2_veer_wrapper.sv:390:- // ICache export interface design/el2_veer_wrapper.sv:391:- el2_mem_if.veer_icache_src el2_icache_export, design/el2_veer_wrapper.sv:392:- // all of these test inputs are brought to top-level; must be tied off based on usage by physical design (ie. icache or not, iccm or not, dccm or not) design/el2_veer_wrapper.sv:393:- design/el2_veer_wrapper.sv:394:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, design/el2_veer_wrapper.sv:395:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt, design/el2_veer_wrapper.sv:396:- design/el2_veer_wrapper.sv:397:- input logic timer_int, design/el2_veer_wrapper.sv:398:- input logic soft_int, design/el2_veer_wrapper.sv:399:- input logic [pt.PIC_TOTAL_INT:1] extintsrc_req, design/el2_veer_wrapper.sv:400:- design/el2_veer_wrapper.sv:401:- output logic dec_tlu_perfcnt0, // toggles when slot0 perf counter 0 has an event inc design/el2_veer_wrapper.sv:402:- output logic dec_tlu_perfcnt1, design/el2_veer_wrapper.sv:403:- output logic dec_tlu_perfcnt2, design/el2_veer_wrapper.sv:404:- output logic dec_tlu_perfcnt3, design/el2_veer_wrapper.sv:405:- design/el2_veer_wrapper.sv:406:- // ports added by the soc team design/el2_veer_wrapper.sv:407:- input logic jtag_tck, // JTAG clk design/el2_veer_wrapper.sv:408:- input logic jtag_tms, // JTAG TMS design/el2_veer_wrapper.sv:409:- input logic jtag_tdi, // JTAG tdi design/el2_veer_wrapper.sv:410:- input logic jtag_trst_n, // JTAG Reset design/el2_veer_wrapper.sv:411:- output logic jtag_tdo, // JTAG TDO design/el2_veer_wrapper.sv:412:- output logic jtag_tdoEn, // JTAG Test Data Output enable design/el2_veer_wrapper.sv:413:- design/el2_veer_wrapper.sv:414:- input logic [31:4] core_id, design/el2_veer_wrapper.sv:415:- design/el2_veer_wrapper.sv:416:- // Memory Export Interface design/el2_veer_wrapper.sv:417:- el2_mem_if.veer_sram_src el2_mem_export, design/el2_veer_wrapper.sv:418:- design/el2_veer_wrapper.sv:419:- // external MPC halt/run interface design/el2_veer_wrapper.sv:420:- input logic mpc_debug_halt_req, // Async halt request design/el2_veer_wrapper.sv:421:- input logic mpc_debug_run_req, // Async run request design/el2_veer_wrapper.sv:422:- input logic mpc_reset_run_req, /

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/el2_veer_wrapper.sv:611:- // Since all the signals in this block are tied to constant, we exclude this from coverage analysis design/el2_veer_wrapper.sv:612:- /*verilator coverage_off*/ design/el2_veer_wrapper.sv:613:- wire lsu_axi_awvalid; design/el2_veer_wrapper.sv:614:- wire lsu_axi_awready; design/el2_veer_wrapper.sv:615:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_awid; design/el2_veer_wrapper.sv:616:- wire [31:0] lsu_axi_awaddr; design/el2_veer_wrapper.sv:617:- wire [3:0] lsu_axi_awregion; design/el2_veer_wrapper.sv:618:- wire [7:0] lsu_axi_awlen; design/el2_veer_wrapper.sv:619:- wire [2:0] lsu_axi_awsize; design/el2_veer_wrapper.sv:620:- wire [1:0] lsu_axi_awburst; design/el2_veer_wrapper.sv:621:- wire lsu_axi_awlock; design/el2_veer_wrapper.sv:622:- wire [3:0] lsu_axi_awcache; design/el2_veer_wrapper.sv:623:- wire [2:0] lsu_axi_awprot; design/el2_veer_wrapper.sv:624:- wire [3:0] lsu_axi_awqos; design/el2_veer_wrapper.sv:625:- design/el2_veer_wrapper.sv:626:- design/el2_veer_wrapper.sv:627:- wire lsu_axi_wvalid; design/el2_veer_wrapper.sv:628:- wire lsu_axi_wready; design/el2_veer_wrapper.sv:629:- wire [63:0] lsu_axi_wdata; design/el2_veer_wrapper.sv:630:- wire [7:0] lsu_axi_wstrb; design/el2_veer_wrapper.sv:631:- wire lsu_axi_wlast; design/el2_veer_wrapper.sv:632:- design/el2_veer_wrapper.sv:633:- wire lsu_axi_bvalid; design/el2_veer_wrapper.sv:634:- wire lsu_axi_bready; design/el2_veer_wrapper.sv:635:- wire [1:0] lsu_axi_bresp; design/el2_veer_wrapper.sv:636:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_bid; design/el2_veer_wrapper.sv:637:- design/el2_veer_wrapper.sv:638:- // AXI Read Channels design/el2_veer_wrapper.sv:639:- wire lsu_axi_arvalid; design/el2_veer_wrapper.sv:640:- wire lsu_axi_arready; design/el2_veer_wrapper.sv:641:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_arid; design/el2_veer_wrapper.sv:642:- wire [31:0] lsu_axi_araddr; design/el2_veer_wrapper.sv:643:- wire [3:0] lsu_axi_arregion; design/el2_veer_wrapper.sv:644:- wire [7:0] lsu_axi_arlen; design/el2_veer_wrapper.sv:645:- wire [2:0] lsu_axi_arsize; design/el2_veer_wrapper.sv:646:- wire [1:0] lsu_axi_arburst; design/el2_veer_wrapper.sv:647:- wire lsu_axi_arlock; design/el2_veer_wrapper.sv:648:- wire [3:0] lsu_axi_arcache; design/el2_veer_wrapper.sv:649:- wire [2:0] lsu_axi_arprot; design/el2_veer_wrapper.sv:650:- wire [3:0] lsu_axi_arqos; design/el2_veer_wrapper.sv:651:- design/el2_veer_wrapper.sv:652:- wire lsu_axi_rvalid; design/el2_veer_wrapper.sv:653:- wire lsu_axi_rready; design/el2_veer_wrapper.sv:654:- wire [pt.LSU_BUS_TAG-1:0] lsu_axi_rid; design/el2_veer_wrapper.sv:655:- wire [63:0] lsu_axi_rdata; design/el2_veer_wrapper.sv:656:- wire [1:0] lsu_axi_rresp; design/el2_veer_wrapper.sv:657:- wire lsu_axi_rlast; design/el2_veer_wrapper.sv:658:- design/el2_veer_wrapper.sv:659:- assign lsu_axi_awready = '0; design/el2_veer_wrapper.sv:660:- assign lsu_axi_wready = '0; design/el2_veer_wrapper.sv:661:- assign lsu_axi_bvalid = '0; design/el2_veer_wrapper.sv:662:- assign lsu_axi_bresp = '0; d

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_ic_mem.sv:21:-import el2_pkg::*; design/ifu/el2_ifu_ic_mem.sv:22:- #( design/ifu/el2_ifu_ic_mem.sv:23:-`include "el2_param.vh" design/ifu/el2_ifu_ic_mem.sv:24:- ) design/ifu/el2_ifu_ic_mem.sv:25:- ( design/ifu/el2_ifu_ic_mem.sv:26:- input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK. design/ifu/el2_ifu_ic_mem.sv:27:- input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in. design/ifu/el2_ifu_ic_mem.sv:28:- input logic rst_l, // reset, active low design/ifu/el2_ifu_ic_mem.sv:29:- input logic clk_override, // Override non-functional clock gating design/ifu/el2_ifu_ic_mem.sv:30:- input logic dec_tlu_core_ecc_disable, // Disable ECC checking design/ifu/el2_ifu_ic_mem.sv:31:- design/ifu/el2_ifu_ic_mem.sv:32:- input logic [31:1] ic_rw_addr, design/ifu/el2_ifu_ic_mem.sv:33:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_wr_en , // Which way to write design/ifu/el2_ifu_ic_mem.sv:34:- input logic ic_rd_en , // Read enable design/ifu/el2_ifu_ic_mem.sv:35:- input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. design/ifu/el2_ifu_ic_mem.sv:36:- input logic ic_debug_rd_en, // Icache debug rd design/ifu/el2_ifu_ic_mem.sv:37:- input logic ic_debug_wr_en, // Icache debug wr design/ifu/el2_ifu_ic_mem.sv:38:- input logic ic_debug_tag_array, // Debug tag array design/ifu/el2_ifu_ic_mem.sv:39:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. design/ifu/el2_ifu_ic_mem.sv:40:- input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. design/ifu/el2_ifu_ic_mem.sv:41:- input logic ic_sel_premux_data, // Select the pre_muxed data design/ifu/el2_ifu_ic_mem.sv:42:- design/ifu/el2_ifu_ic_mem.sv:43:- input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC design/ifu/el2_ifu_ic_mem.sv:44:- output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/ifu/el2_ifu_ic_mem.sv:45:- output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/ifu/el2_ifu_ic_mem.sv:46:- output logic [25:0] ictag_debug_rd_data,// Debug icache tag. design/ifu/el2_ifu_ic_mem.sv:47:- input logic [70:0] ic_debug_wr_data, // Debug wr cache. design/ifu/el2_ifu_ic_mem.sv:48:- design/ifu/el2_ifu_ic_mem.sv:49:- output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank design/ifu/el2_ifu_ic_mem.sv:50:- output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, // ecc error per bank design/ifu/el2_ifu_ic_mem.sv:51:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_tag_valid, // Valid from the I$ tag valid outside (in flops). design/ifu/el2_ifu_ic_mem.sv:52:- design/ifu/el2_ifu_ic_mem.sv:53:- el2_mem_if.veer_icache_src icache_export, design/ifu/el2_ifu_ic_mem.sv:54:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc design/ifu/el2_ifu_ic_mem.sv:55:- input el2_ic_tag_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0]

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_ic_mem.sv:95:-`include "el2_param.vh" design/ifu/el2_ifu_ic_mem.sv:96:- ) design/ifu/el2_ifu_ic_mem.sv:97:- ( design/ifu/el2_ifu_ic_mem.sv:98:- input logic clk, design/ifu/el2_ifu_ic_mem.sv:99:- input logic active_clk, design/ifu/el2_ifu_ic_mem.sv:100:- input logic rst_l, design/ifu/el2_ifu_ic_mem.sv:101:- input logic clk_override, design/ifu/el2_ifu_ic_mem.sv:102:- design/ifu/el2_ifu_ic_mem.sv:103:- input logic [31:1] ic_rw_addr, design/ifu/el2_ifu_ic_mem.sv:104:- input logic [pt.ICACHE_NUM_WAYS-1:0]ic_wr_en, design/ifu/el2_ifu_ic_mem.sv:105:- input logic ic_rd_en, // Read enable design/ifu/el2_ifu_ic_mem.sv:106:- design/ifu/el2_ifu_ic_mem.sv:107:- input logic [pt.ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC design/ifu/el2_ifu_ic_mem.sv:108:- output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/ifu/el2_ifu_ic_mem.sv:109:- input logic [70:0] ic_debug_wr_data, // Debug wr cache. design/ifu/el2_ifu_ic_mem.sv:110:- output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC design/ifu/el2_ifu_ic_mem.sv:111:- output logic [pt.ICACHE_BANKS_WAY-1:0] ic_parerr, design/ifu/el2_ifu_ic_mem.sv:112:- output logic [pt.ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank design/ifu/el2_ifu_ic_mem.sv:113:- input logic [pt.ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. design/ifu/el2_ifu_ic_mem.sv:114:- input logic ic_debug_rd_en, // Icache debug rd design/ifu/el2_ifu_ic_mem.sv:115:- input logic ic_debug_wr_en, // Icache debug wr design/ifu/el2_ifu_ic_mem.sv:116:- input logic ic_debug_tag_array, // Debug tag array design/ifu/el2_ifu_ic_mem.sv:117:- input logic [pt.ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. design/ifu/el2_ifu_ic_mem.sv:118:- input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. design/ifu/el2_ifu_ic_mem.sv:119:- input logic ic_sel_premux_data, // Select the pre_muxed data design/ifu/el2_ifu_ic_mem.sv:120:- design/ifu/el2_ifu_ic_mem.sv:121:- input logic [pt.ICACHE_NUM_WAYS-1:0]ic_rd_hit, design/ifu/el2_ifu_ic_mem.sv:122:- el2_mem_if.veer_icache_src icache_export, design/ifu/el2_ifu_ic_mem.sv:123:- input el2_ic_data_ext_in_pkt_t [pt.ICACHE_NUM_WAYS-1:0][pt.ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt, // this is being driven by the top level for soc testing/etc design/ifu/el2_ifu_ic_mem.sv:124:- // Excluding scan_mode from coverage as its usage is determined by the integrator of the VeeR core. design/ifu/el2_ifu_ic_mem.sv:125:- /*verilator coverage_off*/ design/ifu/el2_ifu_ic_mem.sv:126:- input logic scan_mode design/ifu/el2_ifu_ic_mem.sv:127:- /*verilator coverage_on*/ design/ifu/el2_ifu_ic_mem.sv:128:- design/ifu/el2_ifu_ic_mem.sv:129:- ) ; design/ifu/el2_ifu_ic_mem.sv:130:- design/ifu/el2_ifu_ic_mem.sv:131:- logic [pt.ICACHE_TAG_INDEX_LO-1:1] ic_rw_addr_ff; design/ifu/el2_ifu_ic_mem.sv:132:- logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_wren; //bank x ways design/ifu/el2_ifu_ic_mem.sv:133:- logic [pt.ICACHE_BANKS_WAY-1:0][pt.ICACHE_NUM_WAYS-1:0] ic_b_sb_rden; //bank x ways design/ifu/el2_ifu_ic_mem.sv:134:- design/ifu/el2_ifu_ic_mem.sv:135:- design/ifu/el2_ifu_ic_mem.sv:136:- logic [pt.ICACHE_BANKS_WAY-1:0] ic_b_rden; //bank design/i

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_ic_mem.sv:409:- logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] sel_bypass_data; design/ifu/el2_ifu_ic_mem.sv:410:- logic [pt.ICACHE_BANKS_WAY-1:0] any_bypass; design/ifu/el2_ifu_ic_mem.sv:411:- logic [pt.ICACHE_BANKS_WAY-1:0] any_addr_match; design/ifu/el2_ifu_ic_mem.sv:474:+ logic [pt.ICACHE_BANKS_WAY-1:0][ (71*pt.ICACHE_NUM_WAYS)-1:0] sel_bypass_data; design/ifu/el2_ifu_ic_mem.sv:475:+ logic [pt.ICACHE_BANKS_WAY-1:0] any_bypass; design/ifu/el2_ifu_ic_mem.sv:476:+ logic [pt.ICACHE_BANKS_WAY-1:0] any_addr_match;

[verible-verilog-format] reported by reviewdog 🐶 Raw Output: design/ifu/el2_ifu_ic_mem.sv:413:- // generate IC DATA PACKED SRAMS for 2/4 ways design/ifu/el2_ifu_ic_mem.sv:414:- for (genvar k=0; k<pt.ICACHE_BANKS_WAY; k++) begin: BANKS_WAY // 16B subbank design/ifu/el2_ifu_ic_mem.sv:415:- if (pt.ICACHE_ECC) begin : ECC1 design/ifu/el2_ifu_ic_mem.sv:416:- logic [pt.ICACHE_BANKS_WAY-1:0] [(71*pt.ICACHE_NUM_WAYS)-1:0] wb_packeddout, ic_b_sb_bit_en_vec, wb_packeddout_pre; // data and its bit enables design/ifu/el2_ifu_ic_mem.sv:478:+ // generate IC DATA PACKED SRAMS for 2/4 ways design/ifu/el2_ifu_ic_mem.sv:479:+ for (genvar k = 0; k < pt.ICACHE_BANKS_WAY; k++) begin : BANKS_WAY // 16B subbank design/ifu/el2_ifu_ic_mem.sv:480:+ if (pt.ICACHE_ECC) begin : ECC1 design/ifu/el2_ifu_ic_mem.sv:481:+ logic [pt.ICACHE_BANKS_WAY-1:0][(71*pt.ICACHE_NUM_WAYS)-1:0] design/ifu/el2_ifu_ic_mem.sv:482:+ wb_packeddout, ic_b_sb_bit_en_vec, wb_packeddout_pre; // data and its bit enables