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  1. 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation Public

    The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Ari…

    Verilog

  2. Design-and-Simulation-of-NMOS-Based-OR-Gate Design-and-Simulation-of-NMOS-Based-OR-Gate Public

    Two input OR gate using NMOS load and NMOS as a driver with a Propagation Delay of 2 ns

  3. pid-control-Algorithm-in-verilog pid-control-Algorithm-in-verilog Public

    Developed a Verilog HDL-based PID control algorithm to enhance system stability, processing inputs like clock, reset, setpoint,feedback, and PID gains (Kp, Ki, Kd) to generate a control signal.

    Verilog