Add DIMC and CGRA blocks #52
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Bump @Konste11ation and @IveanEx @Konste11ation when you synthesize, could you please use the Also before doing |
Okie. After passing the CI I will try to run the synthesis with 4 clusters and the extra 32 GPIO pads. |
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Thanks @Konste11ation and @IveanEx ! |
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* cfg: update hemaia configs * cfg: add snax cgra * cfg: add snax dimc * cfg: add hemaia tapeout version * cfg: replace unverilatable cgra * cfg: typo * cfg: update order of clusters * cfg: update order for hemaia_tapeout * cfg: change mem size to 128kb * cfg: update register count for gemmXdma * cfg: fix user width
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* cfg: update hemaia configs * cfg: add snax cgra * cfg: add snax dimc * cfg: add hemaia tapeout version * cfg: replace unverilatable cgra * cfg: typo * cfg: update order of clusters * cfg: update order for hemaia_tapeout * cfg: change mem size to 128kb * cfg: update register count for gemmXdma * cfg: fix user width Co-authored-by: Ryan Antonio <[email protected]>
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This PR adds the DIMC and CGRA modules.
Major TODO:
NOTE:
There is a big problem with the CGRA built with HLS. The SV constructs for pack and unpacked ports are not valid for Verilator. It only works for Questa. I verified that the CGRA builds and synthesizes (got results for it). But Verilator itself does not compile. This should work though.