Add DIMC and CGRA blocks

target/rtl/cfg/cluster_cfg/snax_KUL_cluster.hjson

@@ -20,7 +20,7 @@
         data_width: 64,
         user_width: 3,
         tcdm: {
-            size: 512,                  // 128K -> 512K
+            size: 128,                  // 128K -> 512K
             banks: 32,
         },
         cluster_periph_size: 64, // kB

target/rtl/cfg/cluster_cfg/snax_KUL_xdma_cluster.hjson

@@ -20,7 +20,7 @@
         data_width: 64,
         user_width: 3,
         tcdm: {
-            size: 512,                  // 128K -> 512K
+            size: 128,                  // 128K -> 512K
             banks: 32,
         },
         cluster_periph_size: 64, // kB
@@ -121,11 +121,7 @@
             bender_target: ["snax_gemmX"],
             snax_narrow_tcdm_ports: 8,
             snax_wide_tcdm_ports: 48,
-            snax_gemmx_mesh_row: 8,
-            snax_gemmx_tile_size: 8,
-            snax_gemmx_mesh_col: 8,
-            with_pipeline: false,
-            snax_num_rw_csr: 10,
+            snax_num_rw_csr: 19,
             snax_num_ro_csr: 2,
             snax_gemmx_mesh_row: 8,
             snax_gemmx_tile_size: 8,

target/rtl/cfg/cluster_cfg/snax_alu_cluster.hjson

@@ -20,7 +20,7 @@
         data_width: 64,
         user_width: 3,
         tcdm: {
-            size: 512,                  // 128K -> 512K
+            size: 128,                  // 128K -> 512K
             banks: 32,
         },
         cluster_periph_size: 64, // kB

target/rtl/cfg/cluster_cfg/snax_cgra_cluster.hjson

@@ -0,0 +1,170 @@
+// Copyright 2024 KU Leuven.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Cluster configuration for a simple testbench system.
+{
+    nr_s1_quadrant: 1,
+    s1_quadrant: {
+        nr_clusters: 1,
+    },
+
+    cluster: {
+        name: "snax_cgra_cluster",
+        bender_target: ["snax_cgra_cluster"],
+        boot_addr: 4096, // 0x1000
+        cluster_base_addr: 268435456,  // 0x1000_0000
+        cluster_base_offset: 1048576,  // 256KB -> 1MB
+        cluster_base_hartid: 1,
+        addr_width: 48,
+        data_width: 64,
+        user_width: 3,
+        tcdm: {
+            size: 128,
+            banks: 32,
+        },
+        cluster_periph_size: 64, // kB
+        zero_mem_size: 64, // kB
+        dma_data_width: 512,
+        dma_axi_req_fifo_depth: 3,
+        dma_req_fifo_depth: 3,
+
+        // Additional parameters for Hemaia integration
+        narrow_trans: 4,
+        wide_trans: 32,
+        dma_user_width: 1,
+        // We don't need Snitch debugging in Hemaia
+        enable_debug: false,
+        // We don't need Snitch (core-internal) virtual memory support
+        vm_support: false,
+        // Memory configuration inputs
+        sram_cfg_expose: true,
+        sram_cfg_fields: {
+            ema: 3,
+            emaw: 2,
+            emas: 1
+        },
+
+        // Timing parameters
+        timing: {
+            lat_comp_fp32: 3,
+            lat_comp_fp64: 3,
+            lat_comp_fp16: 2,
+            lat_comp_fp16_alt: 2,
+            lat_comp_fp8: 1,
+            lat_comp_fp8_alt: 1,
+            lat_noncomp: 1,
+            lat_conv: 1,
+            lat_sdotp: 2,
+            fpu_pipe_config: "BEFORE"
+            narrow_xbar_latency: "CUT_ALL_PORTS",
+            wide_xbar_latency: "CUT_ALL_PORTS",
+            // Isolate the core.
+            register_core_req: true,
+            register_core_rsp: true,
+            register_offload_req: true,
+            register_offload_rsp: true,
+            register_ext_narrow: true,
+            register_ext_wide: true,
+        },
+        hives: [
+            // Hive 0
+            {
+                icache: {
+                    size: 8, // total instruction cache size in kByte
+                    sets: 2, // number of ways
+                    cacheline: 256 // word size in bits
+                },
+                cores: [
+                    { $ref: "#/snax_cgra_core_template" },
+                    { $ref: "#/dma_core_template" },
+                ]
+            }
+        ]
+    },
+    dram: {
+        // 0x8000_0000
+        address: 2147483648,
+        // 0x8000_0000
+        length: 2147483648
+    },
+    peripherals: {
+        clint: {
+            // 0xffff_0000
+            address: 4294901760,
+            // 0x0000_1000
+            length: 4096
+        },
+    },
+    // SNAX Accelerator Core Templates
+    snax_cgra_core_template: {
+        isa: "rv32ima",
+        xssr: false,
+        xfrep: false,
+        xdma: false,
+        xf16: false,
+        xf16alt: false,
+        xf8: false,
+        xf8alt: false,
+        xfdotp: false,
+        xfvec: false,
+        snax_acc_cfg: {
+            snax_acc_name: "snax_cgra",
+            bender_target: ["cgra"],
+            snax_narrow_tcdm_ports: 16,
+            snax_num_rw_csr: 1,
+            snax_num_ro_csr: 4,
+            snax_streamer_cfg: {$ref: "#/snax_cgra_streamer_template" }
+        },
+        snax_use_custom_ports: false,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+        // Enable division/square root unit
+        // Xdiv_sqrt: true,
+    },
+    dma_core_template: {
+        isa: "rv32ima",
+        // Xdiv_sqrt: true,
+        # isa: "rv32ema",
+        xdma: true
+        xssr: false
+        xfrep: false
+        xf16: false,
+        xf16alt: false,
+        xf8: false,
+        xf8alt: false,
+        xfdotp: false,
+        xfvec: false,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+    }
+    // SNAX Streamer Templates
+    snax_cgra_streamer_template :{
+
+        data_reader_params: {
+            spatial_bounds: [[1], [1], [1], [1], [1], [1], [1], [1]],
+            temporal_dim: [2, 2, 2, 2, 2, 2, 2, 2],
+            num_channel: [1, 1, 1, 1, 1, 1, 1, 1],
+            fifo_depth: [8, 8, 8, 8, 8, 8, 8, 8],
+        },
+
+        data_writer_params: {
+            spatial_bounds: [[1], [1], [1], [1], [1], [1], [1], [1]],
+            temporal_dim: [2, 2, 2, 2, 2, 2, 2, 2],
+            num_channel: [1, 1, 1, 1, 1, 1, 1, 1],
+            fifo_depth: [8, 8, 8, 8, 8, 8, 8, 8],
+        },
+
+        snax_library_name: "snax-cgra",
+    }
+}

target/rtl/cfg/cluster_cfg/snax_dimc_cluster.hjson

@@ -0,0 +1,171 @@
+// Copyright 2024 KU Leuven.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Cluster configuration for a simple testbench system.
+{
+    nr_s1_quadrant: 1,
+    s1_quadrant: {
+        nr_clusters: 1,
+    },
+
+    cluster: {
+        name: "snax_dimc_cluster",
+        bender_target: ["snax_dimc_cluster"],
+        boot_addr: 4096, // 0x1000
+        cluster_base_addr: 268435456,  // 0x1000_0000
+        cluster_base_offset: 1048576,  // 256KB -> 1MB
+        cluster_base_hartid: 1,
+        addr_width: 48,
+        data_width: 64,
+        user_width: 3,
+        tcdm: {
+            size: 128,
+            banks: 32,
+        },
+        cluster_periph_size: 64, // kB
+        zero_mem_size: 64, // kB
+        dma_data_width: 512,
+        dma_axi_req_fifo_depth: 16,
+        dma_req_fifo_depth: 8,
+
+        // Additional parameters for Hemaia integration
+        narrow_trans: 4,
+        wide_trans: 32,
+        dma_user_width: 1,
+        // We don't need Snitch debugging in Hemaia
+        enable_debug: false,
+        // We don't need Snitch (core-internal) virtual memory support
+        vm_support: false,
+        // Memory configuration inputs
+        sram_cfg_expose: true,
+        sram_cfg_fields: {
+            ema: 3,
+            emaw: 2,
+            emas: 1
+        },
+        // Timing parameters
+        timing: {
+            lat_comp_fp32: 3,
+            lat_comp_fp64: 3,
+            lat_comp_fp16: 2,
+            lat_comp_fp16_alt: 2,
+            lat_comp_fp8: 1,
+            lat_comp_fp8_alt: 1,
+            lat_noncomp: 1,
+            lat_conv: 1,
+            lat_sdotp: 2,
+            fpu_pipe_config: "BEFORE"
+            narrow_xbar_latency: "CUT_ALL_PORTS",
+            wide_xbar_latency: "CUT_ALL_PORTS",
+            // Isolate the core.
+            register_core_req: true,
+            register_core_rsp: true,
+            register_offload_req: true,
+            register_offload_rsp: true,
+            register_ext_narrow: true,
+            register_ext_wide: true,
+        },
+        hives: [
+            // Hive 0
+            {
+                icache: {
+                    size: 8, // total instruction cache size in kByte
+                    sets: 2, // number of ways
+                    cacheline: 256 // word size in bits
+                },
+                cores: [
+                    { $ref: "#/snax_dimc_core_template" },
+                    { $ref: "#/dma_core_template" },
+                ]
+            }
+        ]
+    },
+    dram: {
+        // 0x8000_0000
+        address: 2147483648,
+        // 0x8000_0000
+        length: 2147483648
+    },
+    peripherals: {
+        clint: {
+            // 0xffff_0000
+            address: 4294901760,
+            // 0x0000_1000
+            length: 4096
+        },
+    },
+    // SNAX Accelerator Core Templates
+    snax_dimc_core_template: {
+        isa: "rv32ima",
+        xssr: false,
+        xfrep: false,
+        xdma: false,
+        xf16: false,
+        xf16alt: false,
+        xf8: false,
+        xf8alt: false,
+        xfdotp: false,
+        xfvec: false,
+        snax_acc_cfg: {
+            snax_acc_name: "snax_dimc",
+            bender_target: ["dimc"],
+            snax_wide_tcdm_ports: 40,
+            snax_num_rw_csr: 8,
+            snax_num_ro_csr: 0,
+            snax_disable_csr_manager: true,
+            snax_streamer_cfg: {$ref: "#/snax_dimc_streamer_template" }
+        },
+        snax_use_custom_ports: false,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+        // Enable division/square root unit
+        // Xdiv_sqrt: true,
+    },
+    dma_core_template: {
+        isa: "rv32ima",
+        // Xdiv_sqrt: true,
+        # isa: "rv32ema",
+        xdma: true
+        xssr: false
+        xfrep: false
+        xf16: false,
+        xf16alt: false,
+        xf8: false,
+        xf8alt: false,
+        xfdotp: false,
+        xfvec: false,
+        num_int_outstanding_loads: 1,
+        num_int_outstanding_mem: 4,
+        num_fp_outstanding_loads: 4,
+        num_fp_outstanding_mem: 4,
+        num_sequencer_instructions: 16,
+        num_dtlb_entries: 1,
+        num_itlb_entries: 1,
+    }
+    // SNAX Streamer Templates
+    snax_dimc_streamer_template :{
+
+        data_reader_params: {
+            spatial_bounds: [[8], [8], [8], [8]],
+            temporal_dim: [2, 2, 2, 2],
+            num_channel: [8, 8, 8, 8],
+            fifo_depth: [4, 4, 4, 4],
+        },
+
+        data_writer_params:{
+            spatial_bounds: [[8]],
+            temporal_dim: [2],
+            num_channel: [8],
+            fifo_depth: [4],
+        },
+
+        snax_library_name: "dimc",
+
+    }
+}

target/rtl/cfg/cluster_cfg/snax_hypercorex_cluster.hjson

@@ -20,7 +20,7 @@
         data_width: 64,
         user_width: 3,
         tcdm: {
-            size: 512,                  // 128K -> 512K
+            size: 128,                  // 128K -> 512K
             banks: 32,
         },
         cluster_periph_size: 64, // kB