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soc: arm: nxp_s32: s32k1: improve code cache init #66161

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merged 2 commits into from
Dec 8, 2023
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soc: arm: nxp_s32: s32k1: improve code cache init #66161

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b85d42a
soc: arm: nxp_s32: s32k1: fix code cache init
manuargue Dec 5, 2023
c6c2bc3
soc: arm: nxp_s32: s32k1: use HAL to init code cache
manuargue Dec 5, 2023
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11 changes: 11 additions & 0 deletions soc/arm/nxp_s32/s32k1/Kconfig.soc
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Original file line number Diff line number Diff line change
Expand Up @@ -20,36 +20,42 @@ config SOC_S32K142
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

config SOC_S32K142W
bool "S32K142W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

config SOC_S32K144
bool "S32K144"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

config SOC_S32K144W
bool "S32K144W"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

config SOC_S32K146
bool "S32K146"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

config SOC_S32K148
bool "S32K148"
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select HAS_MCUX_CACHE

endchoice

Expand Down Expand Up @@ -431,4 +437,9 @@ config NXP_S32_FLASH_CONFIG_FDPROT

endif # NXP_S32_FLASH_CONFIG

config NXP_S32_ENABLE_CODE_CACHE
bool "Code cache"
default y
depends on HAS_MCUX_CACHE

endif # SOC_SERIES_S32K1XX
18 changes: 6 additions & 12 deletions soc/arm/nxp_s32/s32k1/soc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,10 @@
#include <cmsis_core.h>
#include <OsIf.h>

#if defined(CONFIG_HAS_MCUX_CACHE)
#include <fsl_cache.h>
#endif

#if defined(CONFIG_WDOG_INIT)
#define WDOG_UPDATE_KEY 0xD928C520U

Expand Down Expand Up @@ -63,18 +67,8 @@ static int soc_init(void)
IP_MPU->CESR = tmp;
#endif /* !CONFIG_ARM_MPU */

#if defined(CONFIG_DCACHE) && defined(CONFIG_ICACHE)
/* Invalidate all ways */
IP_LMEM->PCCCR |= LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK;
IP_LMEM->PCCCR |= LMEM_PCCCR_GO_MASK;

/* Wait until the command completes */
while (IP_LMEM->PCCCR & LMEM_PCCCR_GO_MASK) {
;
}

/* Enable cache */
IP_LMEM->PCCCR |= (LMEM_PCCCR_ENCACHE_MASK);
#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE)
L1CACHE_EnableCodeCache();
barrier_isync_fence_full();
#endif

Expand Down
2 changes: 1 addition & 1 deletion west.yml
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Expand Up @@ -193,7 +193,7 @@ manifest:
groups:
- hal
- name: hal_nxp
revision: d0c424e1c6ef0acac3099a07280a46a24951a47a
revision: 1b2f3608ab0d5f2cf2a4c2973ae9f6353fb43e72
path: modules/hal/nxp
groups:
- hal
Expand Down
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