This repository has been archived by the owner on Sep 18, 2019. It is now read-only.
Changelog
Bug fixes
- fixed an internal generation issue #55
- fixed an absoulte address offset bug in the verilog generator #56
- fixed a bug in the onEachAttribute function in the RFG API #63
- fixed a generator bug in windows enviroment #64
- fixed a bug where reserved fields were not generated in the anot XML generator #71
- for repeated registerfiles only one define should be generated #78
- removed registers from rfg header which were wrongly introduced #79
- fixed a hierarchical naming bug #81
- fixed an absoulte address calculation bug in the verilog generator #82
Enhancements
- added trigger widths in the header generator #60
- package require cleanup for ITCL4.0 support #62
- repeated externals now only generate one verilog file #76
- implemented user defined naming for the rfg header generator #80
Features
- Added a Travis CI build enviroment #74