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Releases: unihd-cag/odfi-rfg
Releases · unihd-cag/odfi-rfg
RFG v1.1.1
Changelog
Bug fixes
- fixed an internal generation issue #55
- fixed an absoulte address offset bug in the verilog generator #56
- fixed a bug in the onEachAttribute function in the RFG API #63
- fixed a generator bug in windows enviroment #64
- fixed a bug where reserved fields were not generated in the anot XML generator #71
- for repeated registerfiles only one define should be generated #78
- removed registers from rfg header which were wrongly introduced #79
- fixed a hierarchical naming bug #81
- fixed an absoulte address calculation bug in the verilog generator #82
Enhancements
- added trigger widths in the header generator #60
- package require cleanup for ITCL4.0 support #62
- repeated externals now only generate one verilog file #76
- implemented user defined naming for the rfg header generator #80
Features
- Added a Travis CI build enviroment #74
wontfix
RFG v1.1.0
RFG v1.1.0-beta1
Changelog
Bug fixes
- software ro/wo invalid address behavior #45, #14
- address calculation bug over register file hierarchies #43
- fixed an naming issue for reserved fields #31
- correct generation for wire/reg signals for external RAMs #29
- handling of groups for rfsbackport generator #21
- correct generation of RWIDTH and WWIDTH defines #17
- RegisterFile with one RAM and software rw permissions #13
Enhancements
- software ro/wo invalid address behavior #45
- optimised VerilogGenerator output #26, #32, #2
- refactored VerilogGenerator #26
- sane Address Map in generated Verilog Code #20
- added relative addresses as attribute #19
- new general generator architecture #18
- optional generation of ifdef for the reset in generated verilog #3
Features
- edge triggered counters #39
- added address aligner #11
- added first e-language generator #9
- added external ramBlocks #6
- added internal RegisterFiles #1
wontfix
- confusing bit-range in signals within RF #28