Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Tools: Tune: Add tplg2 support to dcblock setup tool #8122

Merged
merged 3 commits into from
Sep 14, 2023
Merged

Tools: Tune: Add tplg2 support to dcblock setup tool #8122

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
e24e46b
Tools: Tune: Add tplg2 support to dcblock setup tool
singalsu Aug 29, 2023
599e2e5
Tools: Tune: dcblock: Avoid warning about ignoring imaginary
singalsu Aug 29, 2023
522048b
Tools: Tune: dcblock: Fixes for Matlab compatibility
singalsu Aug 29, 2023
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 9 additions & 6 deletions tools/tune/dcblock/dcblock_build_blob.m
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,12 +1,15 @@
function blob8 = dcblock_build_blob(R_coeffs, endian)
function blob8 = dcblock_build_blob(R_coeffs, endian, ipc_ver)

%% Settings
bits_R = 32; %Q2.30
qy_R = 30;

if nargin < 2
endian = 'little'
endif
endian = 'little';
end
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

bits_R looks like unused.

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yep, I can remove. Easy to add back if would be needed again.


if nargin < 3
ipc_ver = 3;
end

%% Shift values for little/big endian
switch lower(endian)
Expand All @@ -24,7 +27,7 @@

%% Build Blob
data_size = (num_of_coeffs)*4;
[abi_bytes, abi_size] = dcblock_get_abi(data_size);
[abi_bytes, abi_size] = get_abi(data_size, ipc_ver);

blob_size = data_size + abi_size;
blob8 = uint8(zeros(1, blob_size));
Expand All @@ -40,7 +43,7 @@
j=j+4;
end

endfunction
end

function bytes = word2byte(word, sh)
bytes = uint8(zeros(1,4));
Expand Down
17 changes: 0 additions & 17 deletions tools/tune/dcblock/dcblock_get_abi.m
View file
Open in desktop

This file was deleted.

4 changes: 2 additions & 2 deletions tools/tune/dcblock/dcblock_plot_stepfn.m
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
function dcblock_plot_stepfn(R, fs);
function dcblock_plot_stepfn(R, fs)
% Plot the step response of a DC Blocking Filter
% For a DC Blocking filter: H(z) = (1-1/z)/(1 - R/z)
% Therefore the coefficients are b = [1 -1], a = [1 -R]
Expand All @@ -13,4 +13,4 @@
tstr = sprintf("DC Blocking Filter Step Response, R = %i", R);
title(tstr);

endfunction
end
6 changes: 3 additions & 3 deletions tools/tune/dcblock/dcblock_plot_transferfn.m
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
function dcblock_plot_transferfn(R, fs);
function dcblock_plot_transferfn(R, fs)
% Plot the transfer function.
% For a DC Blocking filter: H(z) = (1-1/z)/(1 - R/z)
% Therefore the coefficients are b = [1 -1], a = [1 -R]
Expand All @@ -7,11 +7,11 @@

f = linspace(1, fs/2, 500);

semilogx(f, 20*log10(freqz(b, a, f, fs)));
semilogx(f, 20*log10(abs(freqz(b, a, f, fs))));
grid on
xlabel('Frequency (Hz)');
ylabel('Magnitude (dB)');
tstr = sprintf("DC Blocking Filter Frequency Response, R = %i", R);
title(tstr);

endfunction
end
28 changes: 18 additions & 10 deletions tools/tune/dcblock/example_dcblock.m
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,30 +1,38 @@
function example_dcblock();
function example_dcblock()

% Set the parameters here
tplg_fn = "../../topology/topology1/m4/dcblock_coef_default.m4" % Control Bytes File
tplg1_fn = "../../topology/topology1/m4/dcblock_coef_default.m4"; % Control Bytes File
tplg2_fn = "../../topology/topology2/include/components/dcblock/default.conf";
% Use those files with sof-ctl to update the component's configuration
blob_fn = "../../ctl/dcblock_coef.blob" % Blob binary file
alsa_fn = "../../ctl/dcblock_coef.txt" % ALSA CSV format file
blob3_fn = "../../ctl/ipc3/dcblock_coef.blob"; % Blob binary file
alsa3_fn = "../../ctl/ipc3/dcblock_coef.txt"; % ALSA CSV format file
blob4_fn = "../../ctl/ipc4/dcblock_coef.blob"; % Blob binary file
alsa4_fn = "../../ctl/ipc4/dcblock_coef.txt"; % ALSA CSV format file

endian = "little";
R_coeffs = [0.98, 0.98, 0.98, 0.98, 0.98, 0.98, 0.98, 0.98];

addpath ./../common

blob8 = dcblock_build_blob(R_coeffs, endian);
blob8_ipc4 = dcblock_build_blob(R_coeffs, endian, 4);

% Generate output files
addpath ./../common
tplg_write(tplg1_fn, blob8, "DCBLOCK");
blob_write(blob3_fn, blob8);
alsactl_write(alsa3_fn, blob8);

tplg_write(tplg_fn, blob8, "DCBLOCK");
blob_write(blob_fn, blob8);
alsactl_write(alsa_fn, blob8);
tplg2_write(tplg2_fn, blob8_ipc4, "dcblock_config", "Exported with script example_dcblock.m");
blob_write(blob4_fn, blob8_ipc4);
alsactl_write(alsa4_fn, blob8_ipc4);

% Plot Filter's Transfer Function and Step Response
% As an example, plot the graphs of the first coefficient
fs = 48e3
fs = 48e3;
dcblock_plot_transferfn(R_coeffs(1), fs);
figure
dcblock_plot_stepfn(R_coeffs(1), fs);

rmpath ./../common

endfunction
end
Loading