GitHub - talhaiqbal-10xe/CFA

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
.gitignore		.gitignore
0701.wcfg		0701.wcfg
0718.wcfg		0718.wcfg
CFA_1.v		CFA_1.v
CFA_1_bufferComparison.wcfg		CFA_1_bufferComparison.wcfg
CFA_1_greenInterpolation.wcfg		CFA_1_greenInterpolation.wcfg
CFA_1_tb.m		CFA_1_tb.m
CFA_1_tb.v		CFA_1_tb.v
CFA_1_tb2.v		CFA_1_tb2.v
CFA_1_tb_main.wcfg		CFA_1_tb_main.wcfg
CFA_2.v		CFA_2.v
CFA_2_tb.v		CFA_2_tb.v
CFA_2_wave1.wcfg		CFA_2_wave1.wcfg
CFA_2_wave2.wcfg		CFA_2_wave2.wcfg
CFA_2_wave3.wcfg		CFA_2_wave3.wcfg
CFA_RTL.xise		CFA_RTL.xise
CFA_addressingBayerWave.wcfg		CFA_addressingBayerWave.wcfg
CFA_buffer.wcfg		CFA_buffer.wcfg
CFA_main2.wcfg		CFA_main2.wcfg
DaddaMultiplier.v		DaddaMultiplier.v
DecText2Bin.m		DecText2Bin.m
FA.v		FA.v
HA.v		HA.v
PE.v		PE.v
RB_on_BR.v		RB_on_BR.v
RB_on_G.v		RB_on_G.v
RB_on_G_sums.v		RB_on_G_sums.v
RB_on_G_sums_tb.txt		RB_on_G_sums_tb.txt
RB_on_G_sums_tb.v		RB_on_G_sums_tb.v
RB_on_G_tb.m		RB_on_G_tb.m
RB_on_G_tb.txt		RB_on_G_tb.txt
RB_on_G_tb.v		RB_on_G_tb.v
RB_on_G_wave.wcfg		RB_on_G_wave.wcfg
ReadMe.txt		ReadMe.txt
SubtractorCell.v		SubtractorCell.v
Untitled2.m		Untitled2.m
abs.v		abs.v
abs_diff.v		abs_diff.v
abs_diff_module.m		abs_diff_module.m
abs_diff_tb.v		abs_diff_tb.v
abs_diff_wave.wcfg		abs_diff_wave.wcfg
absolute_value.v		absolute_value.v
adder.v		adder.v
adder4x12.v		adder4x12.v
adder4x17.v		adder4x17.v
adder4x19.v		adder4x19.v
adder5x12.v		adder5x12.v
adder5x14.v		adder5x14.v
adder5x14_cv.v		adder5x14_cv.v
adder5x16.v		adder5x16.v
adder7x30.v		adder7x30.v
adder8x10.v		adder8x10.v
adder8x12.v		adder8x12.v
adder8x13.v		adder8x13.v
address_gen.v		address_gen.v
address_gen_tb.m		address_gen_tb.m
address_gen_tb.txt		address_gen_tb.txt
address_gen_tb.v		address_gen_tb.v
address_gen_tb_wave.wcfg		address_gen_tb_wave.wcfg
addressing_bayer.v		addressing_bayer.v
addressing_bayer_tb.v		addressing_bayer_tb.v
addressing_bayer_tb_wave.wcfg		addressing_bayer_tb_wave.wcfg
addressing_logic.v		addressing_logic.v
addressing_logic_tb1.v		addressing_logic_tb1.v
addressing_logic_tb1_wave.wcfg		addressing_logic_tb1_wave.wcfg
bayer_color.v		bayer_color.v
bayer_color_tb.v		bayer_color_tb.v
bayer_color_tb_wave.wcfg		bayer_color_tb_wave.wcfg
buffer.m		buffer.m
buffer.v		buffer.v
buffer1d.v		buffer1d.v
buffer1d_tb.v		buffer1d_tb.v
buffer2d_tb.v		buffer2d_tb.v
buffer3d_test.m		buffer3d_test.m
buffer_1d.wcfg		buffer_1d.wcfg
buffer_2d.v		buffer_2d.v
buffer_2d.wcfg		buffer_2d.wcfg
buffer_2d_v2.v		buffer_2d_v2.v
buffer_2d_v3.v		buffer_2d_v3.v
buffer_2d_v3_tb.txt		buffer_2d_v3_tb.txt
buffer_2d_v3_tb.v		buffer_2d_v3_tb.v
buffer_2d_v3_tb2.v		buffer_2d_v3_tb2.v
buffer_2d_vf.v		buffer_2d_vf.v
buffer_nD.v		buffer_nD.v
buffer_nD_1_tb.v		buffer_nD_1_tb.v
buffer_nD_2_tb.v		buffer_nD_2_tb.v
buffer_nD_3_tb.v		buffer_nD_3_tb.v
buffer_tb.v		buffer_tb.v
comparator.v		comparator.v
comparator2_tb.v		comparator2_tb.v
comparator_2.v		comparator_2.v
comparator_tb.v		comparator_tb.v
comparator_waveconfig.wcfg		comparator_waveconfig.wcfg
config1.wcfg		config1.wcfg
conv2d.v		conv2d.v
conv2d_tb.v		conv2d_tb.v
conv2d_tb2.v		conv2d_tb2.v
conv2d_v2.v		conv2d_v2.v
counter.v		counter.v
counter_tb.v		counter_tb.v

Repository files navigation

This project is the main development project made on Xilinx ISE 14.7 in which each equation is implemented
and then tested.

In order to simulate a particular module, you need to locate the corresponding test bench (usually module_name_tb.v)
and then run Behavioural Simulation. 

This is not the final submission.