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fpga workflow isn't important, I guess docs #60: Commit 697c4b9 pushed by stevej
November 6, 2024 20:35 2m 4s main
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November 6, 2024 20:35 2m 4s
SystemVerilog and moving to logic docs #59: Commit ffb1bde pushed by stevej
November 6, 2024 20:24 2m 32s main
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November 6, 2024 20:24 2m 32s
moving to always_ff docs #58: Commit f52449f pushed by stevej
November 6, 2024 19:42 2m 21s main
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November 6, 2024 19:42 2m 21s
run fpga workflow on each push docs #57: Commit 5d0d22e pushed by stevej
November 6, 2024 19:21 2m 26s main
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November 6, 2024 19:21 2m 26s
added harden.log to .gitignore docs #56: Commit 83d7021 pushed by stevej
November 6, 2024 19:09 2m 14s main
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November 6, 2024 19:09 2m 14s
remove dead code, formatting and new comment docs #55: Commit 50ce1ee pushed by stevej
November 6, 2024 19:00 2m 7s main
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November 6, 2024 19:00 2m 7s
more SystemVerilog changes and style change for clk docs #54: Commit 7d1fb92 pushed by stevej
November 6, 2024 18:50 2m 27s main
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November 6, 2024 18:50 2m 27s
beginning the full shift to SystemVerilog: change fpga Makefile, use … docs #53: Commit f0e72f1 pushed by stevej
November 6, 2024 18:30 2m 6s main
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November 6, 2024 18:30 2m 6s
use gclk only for formal tests, add it to the bmc options docs #52: Commit dcb2296 pushed by stevej
November 5, 2024 20:16 2m 8s main
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November 5, 2024 20:16 2m 8s
add nettypes, remove been_reset, add better comment docs #51: Commit 2626d77 pushed by stevej
November 5, 2024 19:23 2m 46s main
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November 5, 2024 19:23 2m 46s
formal method to ensure we can leave the TAP FSM docs #50: Commit b28431c pushed by stevej
November 5, 2024 18:10 2m 5s main
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November 5, 2024 18:10 2m 5s
Merge branch 'main' of github.com:stevej/tt09-jtag-example-v2-stevej docs #49: Commit 4d8c202 pushed by stevej
November 5, 2024 17:12 2m 4s main
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November 5, 2024 17:12 2m 4s
Update README.md docs #48: Commit 8400e1a pushed by stevej
November 5, 2024 03:36 2m 30s main
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November 5, 2024 03:36 2m 30s
add debug bits to see how far we're getting in the TAP state machine … docs #47: Commit 9156866 pushed by stevej
November 5, 2024 02:53 2m 7s main
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November 5, 2024 02:53 2m 7s
tell yosys that clk is the global clock docs #46: Commit 5086ef0 pushed by stevej
November 4, 2024 15:28 2m 26s main
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November 4, 2024 15:28 2m 26s
write to TDO on the negative edge. This adds a half-cycle delay to av… docs #45: Commit 4e0398f pushed by stevej
November 4, 2024 15:14 2m 13s main
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November 4, 2024 15:14 2m 13s
TRST being high too early breaks GL simulation docs #44: Commit ef61f98 pushed by stevej
November 2, 2024 22:36 2m 3s main
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November 2, 2024 22:36 2m 3s
explicit widths, switch to one-hot encoding for the TAP state machine docs #43: Commit e317398 pushed by stevej
November 2, 2024 22:27 2m 1s main
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November 2, 2024 22:27 2m 1s
start with TRST and TCK high then low docs #42: Commit e4bbaa9 pushed by stevej
November 2, 2024 19:53 1m 58s main
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November 2, 2024 19:53 1m 58s
fix a fencepost error by setting byte_transmitter_enable high a clock… docs #41: Commit 6ed3c7f pushed by stevej
November 2, 2024 19:42 2m 10s main
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November 2, 2024 19:42 2m 10s
remove mux for simplicity, shuffle some bits around docs #40: Commit e93a080 pushed by stevej
November 2, 2024 04:14 2m 42s main
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November 2, 2024 04:14 2m 42s
fixing current_state to be the right number of bits, fixing an assert… docs #39: Commit 8840286 pushed by stevej
November 1, 2024 23:45 2m 34s main
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November 1, 2024 23:45 2m 34s
tighten up formal tests docs #38: Commit 0e56230 pushed by stevej
November 1, 2024 21:53 2m 13s main
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November 1, 2024 21:53 2m 13s
stripping minipit down to basics docs #37: Commit f5ea9bf pushed by stevej
October 31, 2024 23:08 2m 4s main
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October 31, 2024 23:08 2m 4s
moving some signals into continuous assignment for clarity docs #36: Commit 2331c55 pushed by stevej
October 31, 2024 18:58 2m 7s main
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October 31, 2024 18:58 2m 7s