Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Branch Prediction, and the Five pipeline stages are simulated and verified the functional testing with test benches on ModelSim.
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Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Branch Prediction, and the Five pipeline stages are simulated and verified the functional testing with test benches on ModelSim.
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srpoyrek/RISC-V
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Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Branch Prediction, and the Five pipeline stages are simulated and verified the functional testing with test benches on ModelSim.
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