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1. RISC-V RISC-V Public

   Implementing a five-stage pipeline RSIC-V architecture (RV32I Core instruction set) using Verilog HDL. All the functional modules required including the Hazard detection unit, Forwarding Unit, Bran…

   Verilog 24 3

2. rt_dvfs_simulator rt_dvfs_simulator Public

   Simulation and Comparison Real-Time DVFS scheduling algorithms. Implemented the RT-DVFS scheduling algorithms static voltage scaling and the cycle conserving. Both the techniques were EDF based sch…

   Python 4 3

3. NIVAS NIVAS Public

   Implementation of 1st order Software PLL for Grid Tie Micro Inverter on Micrium RTOS (µC/OS-II) to schedule tasks such as ADC Read Task, PLL Task, SPWM Generation Task using Round Robin Scheduler o…

   HTML 2 1

4. Motion-Planning Motion-Planning Public

   Mathematica

5. pipeline_simulator pipeline_simulator Public

   Integer pipeline simulator includes a forwarding unit, a hazard detection unit with the static branch prediction technique predict not taken. 8-stage pipeline with a 2-stage fetch unit and 3-stage …

   Python

6. portfolio_sp portfolio_sp Public

   Shreyas Poyrekar

   JavaScript