-
Notifications
You must be signed in to change notification settings - Fork 646
Issues: riscv/riscv-isa-manual
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Does riscv allow vector load/store access the same device address multiple times?
#1741
opened Nov 25, 2024 by
AlexGJL
instret, cycle, time outside of Zicntr (and hpmpcounterN outside Zihpm)
#1734
opened Nov 22, 2024 by
dhower-qc
Conflicting exception types caused by misaligned AMO instructions.
#1726
opened Nov 15, 2024 by
jillleon007
Can index-ordered and index-unordered VL*/VS* instructions be used to access device address space?
#1719
opened Nov 9, 2024 by
Steven-Li-Xiaogang
Reason for vstart≥vl requiring undisturbed tail elements even with
ta
vtype
#1715
opened Nov 7, 2024 by
dzaima
When the PM feature is enabled, can PMLEN be set to 7 in sv48 mode?
#1702
opened Oct 30, 2024 by
chara811
What are the sources of memory attributes under different translation mechanisms?
#1699
opened Oct 28, 2024 by
chara811
why are the hstatus.VTSR/VTVM and VTW permission check different?
#1695
opened Oct 23, 2024 by
yinhanquan
Hypervisor chapter uses term HSLEN but I think it means HSXLEN
#1693
opened Oct 22, 2024 by
james-ball-qualcomm
Possibility of 'Environment call from S-mode' delegation to S-mode
#1673
opened Oct 4, 2024 by
evgeniy-paltsev
Previous Next
ProTip!
Follow long discussions with comments:>50.