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Let MXR not affect implicit memory access for VS-stage address translation #1760

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Aug 5, 2024
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Let MXR not affect implicit memory access for VS-stage address translation #1760

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2 changes: 1 addition & 1 deletion riscv/mmu.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -404,7 +404,7 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
int maxgpabits = vm.levels * vm.idxbits + vm.widenbits + PGSHIFT;
reg_t maxgpa = (1ULL << maxgpabits) - 1;

bool mxr = proc->state.sstatus->readvirt(false) & MSTATUS_MXR;
bool mxr = !is_for_vs_pt_addr && (proc->state.sstatus->readvirt(false) & MSTATUS_MXR);
// tinst is set to 0x3000/0x3020 - for RV64 read/write respectively for
// VS-stage address translation (for spike HSXLEN == VSXLEN always) else
// tinst is set to 0x2000/0x2020 - for RV32 read/write respectively for
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