fix error in reading right sstatus

riscv-software-src · Sep 18, 2024 · a8525b6 · a8525b6
1 parent 2e816f2
commit a8525b6
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv/processor.cc b/riscv/processor.cc
@@ -446,7 +446,7 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
   // An unexpected trap - a trap when SDT is 1 - traps to M-mode
   if ((state.prv <= PRV_S && bit < max_xlen) &&
       (((vsdeleg >> bit) & 1)  || ((hsdeleg >> bit) & 1))) {
-    reg_t s = curr_virt ? state.nonvirtual_sstatus->read() : state.sstatus->read();
+    reg_t s = state.sstatus->read();
     supv_double_trap = get_field(s, MSTATUS_SDT);
     if (supv_double_trap)
       vsdeleg = hsdeleg = 0;