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debug: Halted harts can also be unavailable.
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timsifive committed Sep 28, 2023
1 parent 847fe5d commit 7613da4
Showing 1 changed file with 5 additions and 5 deletions.
10 changes: 5 additions & 5 deletions riscv/debug_module.cc
Original file line number Diff line number Diff line change
Expand Up @@ -413,14 +413,14 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value)
dmstatus.allresumeack = false;
}
auto hart = sim->get_harts().at(hart_id);
if (hart_state[hart_id].halted) {
dmstatus.allrunning = false;
dmstatus.anyhalted = true;
dmstatus.allunavail = false;
} else if (!hart_available(hart_id)) {
if (!hart_available(hart_id)) {
dmstatus.allrunning = false;
dmstatus.allhalted = false;
dmstatus.anyunavail = true;
} else if (hart_state[hart_id].halted) {
dmstatus.allrunning = false;
dmstatus.anyhalted = true;
dmstatus.allunavail = false;
} else {
dmstatus.allhalted = false;
dmstatus.anyrunning = true;
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