Fix a typo in f11bd7b

riscv-software-src · Aug 12, 2024 · 20a5082 · 20a5082
1 parent 6f28e4b
commit 20a5082
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv/sim.cc b/riscv/sim.cc
@@ -103,8 +103,8 @@ sim_t::sim_t(const cfg_t *cfg, bool halted,
                                       cfg, this, cfg->hartids[i], halted,
                                       log_file.get(), sout_));
       harts[cfg->hartids[i]] = procs[i];
-      return;
     }
+    return;
   } // otherwise, generate the procs by parsing the DTS
 
   // Only make a CLINT (Core-Local INTerrupt controller) and PLIC (Platform-