Merge pull request #1506 from riscv-software-src/fix-1505

Don't enforce alignment constraints vwsll.v[xi] rs1 arg
riscv-software-src · Dec 11, 2023 · 19078c1 · 19078c1
2 parents f1e0be8 + 874ac59
commit 19078c1
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/riscv/zvk_ext_macros.h b/riscv/zvk_ext_macros.h
@@ -750,7 +750,7 @@
 //  - 'rs1', unsigned, SEW width, by value, constant.
 #define VI_ZVK_VX_WIDENING_ULOOP(BODY) \
   do { \
-    VI_CHECK_DSS(true); \
+    VI_CHECK_DSS(false); \
     VI_LOOP_BASE \
       switch (sew) { \
         case e8: { \
@@ -788,7 +788,7 @@
 //  - 'zimm5', unsigned, SEW width, by value, constant.
 #define VI_ZVK_VI_WIDENING_ULOOP(BODY) \
   do { \
-    VI_CHECK_DSS(true); \
+    VI_CHECK_DSS(false); \
     VI_LOOP_BASE \
       switch (sew) { \
         case e8: { \