Waive Verilator linter for lints not matching our code style

CHANGELOG.md

@@ -4,6 +4,10 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
 and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
 
+## Unreleased
+### Changed
+- Waive Verilator linter for lints not matching our code style
+
 ## 0.2.13 - 2023-09-19
 ### Fixed
 - `tc_sram_xilinx`: Fix be assignment

src/deprecated/pulp_clk_cells.sv

@@ -98,9 +98,9 @@ module pulp_clock_delay(
   input  logic in_i,
   output logic out_o
 );
-
+  /* verilator lint_off ASSIGNDLY */
   assign #(300ps) out_o = in_i;
-
+  /* verilator lint_on ASSIGNDLY */
 endmodule
 `endif
 

src/deprecated/pulp_clock_gating_async.sv

@@ -41,4 +41,4 @@ module pulp_clock_gating_async #(
     .clk_o
   );
 
-endmodule
+endmodule

src/rtl/tc_clk.sv

@@ -43,10 +43,11 @@ module tc_clk_gating #(
 );
 
   logic clk_en;
-
+  /* verilator lint_off COMBDLY */
   always_latch begin
     if (clk_i == 1'b0) clk_en <= en_i | test_en_i;
   end
+  /* verilator lint_on COMBDLY */
 
   assign clk_o = clk_i & clk_en;