hw: Added fpga vregfile #101
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May 22, 2024 in 0s
reviewdog [verible-verilog-lint] report
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Findings (1)
hw/ip/spatz/src/vregfile_fpga.sv|7 col 8| Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
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Check warning on line 7 in hw/ip/spatz/src/vregfile_fpga.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/ip/spatz/src/vregfile_fpga.sv#L7
Declared module does not match the first dot-delimited component of file name: "vregfile_fpga" [Style: file-names] [module-filename]
Raw output
message:"Declared module does not match the first dot-delimited component of file name: \"vregfile_fpga\" [Style: file-names] [module-filename]" location:{path:"hw/ip/spatz/src/vregfile_fpga.sv" range:{start:{line:7 column:8}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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